A low power dual-band multi-mode RF front-end for GNSS applications

A CMOS dual-band multi-mode RF front-end for the global navigation satellite system receivers of all GPS,Bei-Dou,Galileo and Glonass systems is presented.It consists of a reconfigurable low noise amplifier（LNA）,a broadband active balun,a high linearity mixer and a bandgap reference（BGR） circuit.The effect of the input parasitic capacitance on the input impedance of the inductively degenerated common source LNA is analyzed in detail.By using two different LC networks at the input port and the switched capacitor at the output port,the LNA can work at two different frequency bands（1.2 GHz and 1.5 GHz） under low power consumption.The active balun uses a hybrid-connection structure to achieve high bandwidth.The mixer uses the multiple gated transistors technique to acquire a high linearity under low power consumption but does not deteriorate other performances.The measurement results of the proposed front-end achieve a noise figure of 2.1/2.0 dB,a gain of 33.9/33.8 dB and an input 1-dB compression point of 0/1 dBm at 1227.6/1575.42 MHz.The power consumption is about 16 mW under a 1.8 V power supply.

An RF frontend circuit design of a Compass and GPS dual-mode dual-channel image rejection radio receiver

This paper introduces a fully integrated low power consumption radio receiver frontend circuit for a Compass（Beidou） and GPS dual mode dual channel system with 2.5 dB NF,1.02 mm^2 areas,and 8 mA of current in 0.18μm TSMC CMOS process.Except for a few passive components for input matching,other components such as an off-chip low noise amplifier or a balun are not required.With a non-tunable passive image rejection filter,the receiver frontend can achieve around 60 dB gain and 34 dB image rejection.

A 0.8-3 GHz RF-VGA with 35 dB dynamic range in 0.13μm CMOS

A wideband variable gain amplifier （VGA） implemented in 0.13 μm CMOS technology is presented. To optimize noise performance, an active feedback amplifier with 15 dB fixed gain is put in the front, followed by modified Cherry-Hooper amplifiers in cascade providing variable gain, which adopt dual loop feedback for band- width extension. Negative capacitive neutralization and capacitive source degeneration are employed for Miller effect compensation and DC offset cancellation, respectively. Measurement results show that the proposed VGA achieves a 35 dB gain tuning range with an upper 3-dB bandwidth larger than 3 GHz and the input 1 dB compression point of-29 dBm at the lowest gain state, while the minimum noise figure is 9 dB at the highest gain state. The core VGA （without test buffer） consumes 32 mW from 1.2 V power supply and occupies 0.48 mm2 area.

Design of 20-44 GHz broadband doubler MMIC

This paper presents the design and performance of a broadband millimeter-wave frequency doubler MMIC using active 0.15 μm GaAs PHEMT and operating at output frequencies from 20 to 44 GHz. This chip is composed of a single ended-into differential-out active Balun, balanced FETs in push-push configuration, and a distributed amplifier. The MMIC doubler exhibits more than 4 dB conversion gain with 12 dBm of output power, and the fundamental frequency suppression is typically -20 dBc up to 44 GHz. The MMIC works at VDD = 3.5 V, Vss = -3.5 V, Id = 200 mA and the chip size is 1.5× 1.8 mm^2.