Design of CMOS active pixels based on finger-shaped PPD

To improve the full-well capacity and linear dynamic range of CMOS image sensor,a special finger-shaped pinned photodiode(PPD)is designed.In terms of process,the first N-type ion implantation of the PPD N buried layer is extended under the transfer gate,thereby increasing the PPD capacitance.Based on TCAD simulation,the width and spacing of PPD were precisely adjusted.A high full-well capacity pixel design with a pixel size of 6×6μm^2 is realized based on the 0.18μm CMOS process.The simulation results indicate that the pixel with the above structure and process has a depletion depth of 2.8μm and a charge transfer efficiency of 100%.The measurement results of the test chip show that the full-well capacity can reach 68650 e–.Compared with the conventional structure,the proposed PPD structure can effectively improve the full well capacity of the pixel.

Design,Analysis,and Optimization of a CMOS Active Pixel Sensor

A three-transistor active pixel sensor and its double sampling readout circuit implemented by a switch capacitor amplifier are designed. The circuit is embedded in a 64 × 64 pixel array CMOS image sensor and success-fully taped out with a Chartered 0.35μm process. The pixel pitch is 8μm × 8μm with a fill factor of 57%, the photo-sensitivity is 0.8V/（lux · s） ,and the dynamic range is 50dB. Theoretical analysis and test results indicate that as the process is scaled down, a smaller pixel pitch reduces the sensitivity. A deep junction n-well/p-substrate photodiode with a reasonable fill factor and high sensitivity are more appropriate for submicron processes.

Total ionizing dose effects in pinned photodiode complementary metal-oxide-semiconductor transistor active pixel sensor

A pinned photodiode complementary metal–oxide–semiconductor transistor（CMOS） active pixel sensor is exposed to ^60Co to evaluate the performance for space applications. The sample is irradiated with a dose rate of 50 rad（SiO2）/s and a total dose of 100 krad（SiO2）, and the photodiode is kept unbiased. The degradation of dark current, full well capacity,and quantum efficiency induced by the total ionizing dose damage effect are investigated. It is found that the dark current increases mainly from the shallow trench isolation（STI） surrounding the pinned photodiode. Further results suggests that the decreasing of full well capacity due to the increase in the density, is induced by the total ionizing dose（TID） effect, of the trap interface, which also leads to the degradation of quantum efficiency at shorter wavelengths.

Analysis of proton and γ-ray radiation effects on CMOS active pixel sensors

Radiation effects on complementary metal-oxide-semiconductor（CMOS） active pixel sensors（APS） induced by proton and γ-ray are presented. The samples are manufactured with the standards of 0.35 μm CMOS technology. Two samples have been irradiated un-biased by 23 MeV protons with fluences of 1.43 × 10^11 protons/cm^2 and 2.14 × 10^11 protons/cm-2,respectively, while another sample has been exposed un-biased to 65 krad（Si） ^60Co γ-ray. The influences of radiation on the dark current, fixed-pattern noise under illumination, quantum efficiency, and conversion gain of the samples are investigated. The dark current, which increases drastically, is obtained by the theory based on thermal generation and the trap induced upon the irradiation. Both γ-ray and proton irradiation increase the non-uniformity of the signal, but the nonuniformity induced by protons is even worse. The degradation mechanisms of CMOS APS image sensors are analyzed,especially for the interaction induced by proton displacement damage and total ion dose（TID） damage.

MOS-based model of four-transistor CMOS image sensor pixels for photoelectric simulation

By using the MOS-based model established in this paper, the physical process of photoelectron generation, transfer,and storage in the four-transistor active pixel sensor(4 T-APS) pixels can be simulated in SPICE environment. The variable capacitance characteristics of double junctions in pinned photodiodes(PPDs) and the threshold voltage difference formed by channel nonuniform doping in transfer gates(TGs) are considered with this model. The charge transfer process of photogenerated electrons from PPDs to the floating diffusion(FD) is analyzed, and the function of nonuniform doping of TGs in suppressing charge injection back to PPDs is represented with the model. The optical and electrical characteristics of all devices in the pixel are effectively combined with the model. Moreover, the charge transfer efficiency and the voltage variation in PPD can be described with the model. Compared with the hybrid simulation in TCAD and the Verilog-A simulation in SPICE, this model has higher simulation efficiency and accuracy, respectively. The effectiveness of the MOS-based model is experimentally verified in a 3 μm test pixel designed in 0.11 μm CIS process.

New Active Digital Pixel Circuit for CMOS Image Sensor

A new active digital pixel circuit for CMOS image sensor is designed consisting of four components: a photo-transducer, a preamplifier, a sample & hold (S & H) circuit and an A/D converter with an inverter. It is optimized by simulation and adjustment based on 2 μm standard CMOS process. Each circuit of the components is designed with specific parameters. The simulation results of the whole pixel circuits show that the circuit has such advantages as low distortion, low power consumption, and improvement of the output performances by using an inverter.

A New CMOS Image Sensor with a High Fill Factor and the Dynamic Digital Double Sampling Technique

A single CMOS image sensor based on a 0.35μm process along with its design and implementation is introduced. The architecture of an active pixel sensor is used in the chip. The fill factor of a pixel cell can reach 43%,higher than the traditional factor of 30%. Moreover, compared with the conventional method whose fixed pattern noise （FPN） is around 0.5%, a dynamic digital double sampling technique is developed, which possesses simpler circuit architecture and a better FPN suppression outcome. The CMOS image sensor chip is implemented in the 0.35μm mixed signal process of a Chartered by MPW. The experimental results show that the chip operates welt,with an FPN of about 0.17%.

Pixel and Column Fixed Pattern Noise Suppression Mechanism in CMOS Image Sensor

A double sampling circuit to eliminating fixed pattern noise(FPN) in CMOS image sensor (CIS) is presented. Double sampling is implemented by column switch capacitor amplifier directly, and offset compensation is added to the amplifier to suppress column FPN. The amplifier is embedded in a 64×64 CIS and successfully fabricated with chartered 0.35 μm process. Theory analysis and circuit simulation indicate that FPN can be suppressed from millivolt to microvolt. Test results show that FPN is smaller than one least-significant bit of 8 bit ADC. FPN is reduced to an acceptable level with double sampling technique implemented with switch capacitor amplifier.

DESIGN AND IMPLEMENTATION OF CMOS IMAGE SENSOR

A single Complementary Metal Oxide Semiconductor (CMOS) image sensor based on 0.35μm process along with its design and implementation is introduced in this paper. The pixel ar-chitecture of Active Pixel Sensor (APS) is used in the chip,which comprises a 256×256 pixel array together with column amplifiers,scan array circuits,series interface,control logic and Analog-Digital Converter (ADC). With the use of smart layout design,fill factor of pixel cell is 43%. Moreover,a new method of Dynamic Digital Double Sample (DDDS) which removes Fixed Pattern Noise (FPN) is used. The CMOS image sensor chip is implemented based on the 0.35μm process of chartered by Multi-Project Wafer (MPW). This chip performs well as expected.

Brightness Independent 4-Star Matching Algorithm for Lost-in-Space 3-Axis Attitude Acquisition

A star identification algorithm was developed for a charge-coupled device （CCD） or complementary metal-oxide-semiconductor （CMOS） autonomous star tracker to acquire 3-axis attitude information for a lost-in-space spacecraft. The algorithm took advantage of an efficient on-board database and an original “4- star matching” pattern recognition strategy to achieve fast and reliable star identification. The on-board database was composed of a brightness independent guide star catalog （mission catalog） and a K-vector star pair catalog. The star pattern recognition method involved direct location of star pair candidates and a sim- ple array matching procedure. Tests of the algorithm with a CMOS active pixel sensor （APS） star tracker result in a 99.9% success rate for star identification for lost-in-space 3-axis attitude acquisition when the angular measurement accuracy of the star tracker is at least 0.01°. The brightness independent algorithm requires relatively higher measurement accuracy of the star apparent positions that can be easily achieved by CCD or CMOS sensors along with subpixel centroiding techniques.

Wide dynamic range CMOS image sensor with in-pixel double-exposure and synthesis

A wide-dynamic-range CMOS image sensor（CIS） based on synthesis of a long-time and a short-time exposure signal in the floating diffusion（FD） of a five-transistor active pixel is proposed.With optimized pixel operation,the response curve is compressed and a wide dynamic range image is obtained.A prototype wide-dynamic-range CMOS image sensor was developed with a 0.18μm CIS process.With the double exposure time 2.4 ms and 70 ns,the dynamic range of the proposed sensor is 80 dB with 30 frames per second（fps）.The proposed CMOS image sensor meets the demands of applications in security surveillance systems.