MV10 is an MCU which consists of PWM, ADC,CAN and some other function blocks. It is designed for car body＇s control. Advanced peripheral bus （APB） is a low speed AMBA bus connecting low-power peripherals. This pape...MV10 is an MCU which consists of PWM, ADC,CAN and some other function blocks. It is designed for car body＇s control. Advanced peripheral bus （APB） is a low speed AMBA bus connecting low-power peripherals. This paper presents an implementation of APB interface for MV10 MCU. After that, MV10 can be integrated into any AMBA system on chips （SoCs） easily. We have built a multi-core system with ABMA to verify this design, In this system ARM9 is a main processor mounted on AHB and MV10 acts as a low-power and low-speed slaver on APB. Before building this system, some operations are encapsulated into a task with dedicated ID. MV10 works as a co-processor with ARM by acquiring task ID from ARM. The result of simulation indicates that MCU can work well as expected. Based on our design, MV10 can be mounted on any AMBA system from now on.展开更多
With the rapid development of integrated circuit(IC)technology,reusable intelligent property(IP)core design is widely valued by the industry.Based on the in-depth study of the functional characteristics of advanced mi...With the rapid development of integrated circuit(IC)technology,reusable intelligent property(IP)core design is widely valued by the industry.Based on the in-depth study of the functional characteristics of advanced microcontroller bus architecture(AMBA),a design scheme of IP core is presented,and it is divided into the functional modules,and the structural design of the IP core is completed.The relationship between the internal modules of the IP core is clarified,and the top-down design method is used to build the internal architecture of the IP core.The IP core interface module,register module,baud rate module,transmit module,receive module,and interrupt module are designed in detail by using Verilog language.The simulation results show that the designed IP core supports serial peripheral interface(SPI)protocol,the function coverage of IP core reaches 100%,the maximum working frequency reaches 200 MHz,and the resource occupancy rate is less than 15%.The reusable IP core can support multiple data formats,multiple timing transmission modes,and master/slave operation modes,reducing the resource consumption of hardware circuits and having stronger applicability.展开更多
基金supported by the IC Special Foundation of Science and Technology Commission of Shanghai Municipality(Grant No.09706201300)the Shanghai Municipal Commission of Economic and Information(Grant No.090344)the Shanghai High-Technology Industrialization of New Energy Vehicles(Grant No.09625029)
文摘MV10 is an MCU which consists of PWM, ADC,CAN and some other function blocks. It is designed for car body＇s control. Advanced peripheral bus （APB） is a low speed AMBA bus connecting low-power peripherals. This paper presents an implementation of APB interface for MV10 MCU. After that, MV10 can be integrated into any AMBA system on chips （SoCs） easily. We have built a multi-core system with ABMA to verify this design, In this system ARM9 is a main processor mounted on AHB and MV10 acts as a low-power and low-speed slaver on APB. Before building this system, some operations are encapsulated into a task with dedicated ID. MV10 works as a co-processor with ARM by acquiring task ID from ARM. The result of simulation indicates that MCU can work well as expected. Based on our design, MV10 can be mounted on any AMBA system from now on.
文摘With the rapid development of integrated circuit(IC)technology,reusable intelligent property(IP)core design is widely valued by the industry.Based on the in-depth study of the functional characteristics of advanced microcontroller bus architecture(AMBA),a design scheme of IP core is presented,and it is divided into the functional modules,and the structural design of the IP core is completed.The relationship between the internal modules of the IP core is clarified,and the top-down design method is used to build the internal architecture of the IP core.The IP core interface module,register module,baud rate module,transmit module,receive module,and interrupt module are designed in detail by using Verilog language.The simulation results show that the designed IP core supports serial peripheral interface(SPI)protocol,the function coverage of IP core reaches 100%,the maximum working frequency reaches 200 MHz,and the resource occupancy rate is less than 15%.The reusable IP core can support multiple data formats,multiple timing transmission modes,and master/slave operation modes,reducing the resource consumption of hardware circuits and having stronger applicability.
