All-optical clock recovery from 10-Gb/s NRZ data and NRZ to RZ format conversion

A non-return-to-zero （NRZ） to pseudo-return-to-zero （PRZ） converter consisting of a semiconductor optical amplifier （SOA） and an arrayed waveguide grating （AWG） is proposed, by which the enhancement of clock frequency component and clock-to-data suppression ratio of the XRZ data are evidently achieved. All- optical clock recovery from XRZ data at 10 Gb/s is successfully demonstrated with the proposed XRZ-to- PRZ converter and a mode-locked SOA fiber laser. Furthermore, XRZ-to-RZ format conversion of 10 Gb/s is realized bv using the recovered clock as the control light of terahertz optical asymmetric demultiplexer （TOAD）, which further proves that the proposed clock recovery scheme is applicable.

Control of period-one oscillation for all-optical clock division and clock recovery by optical pulse injection driven semiconductor laser

The period-one oscillation produced by an external optical pulse injection driven semiconductor laser is applied to clock recovery and frequency division. By adjusting the repetition rate or injection power of the external injection optical pulses to lock the different harmonic frequencies of the period-one state, the clock recovery and the frequency division （the second and third frequency divisions） are achieved experimentally. In addition, in frequency locking ranges of 2 GHz and 1.9 GHz, the second and third frequency divisions are obtained with the phase noise lower than 100 dBc/Hz, respectively. Our experimental results are consistent well with the numerical simulations.

All-optical clock recovery for 40 Gbaud NRZ-QPSK signals using amplified feedback DFB laser diode

An all-optical clock recovery scheme based on monolithic amplified feedback DFB laser （AFL） diode is proposed for nonreturn-to-zero （NRZ） quadrature phase shift keying （QPSK） format signals. By using a preprocessing stage, clock recovery （CR） is successfully demonstrated for 40-Gbaud NRZ-QPSK signals based on this scheme. The dependence of the timing jitter of the recovered clock on the optical power of the injected signal is investigated. A minimum timing jitter of 362.8 fs （integrated within a frequency range from 10 Hz to 10 MHz） is obtained.

100 Gb/s all-optical clock recovery based on a monolithic dual-mode DBR laser

We experimentally demonstrate all-optical clock recovery for 100 Gb/s return-to-zero on-off keying signals based on a monolithic dual-mode distributed Bragg reflector （DBR） laser, which can realize both mode spacing and wavelength tuning. By using a coherent injection locking scheme, a 100 GHz optical clock can be recovered with a timing jitter of 530 fs, which is derived by an optical sampling oscilloscope from both the phase noise and the power fluctuation. Furthermore, for degraded injection signals with an optical signal-to-noise ratio as low as 4.1 dB and a 25 km long distance transmission, good-quality optical clocks are all successfully recovered.

2.5Gb/s 0.18μm CMOS Clock and Data Recovery Circuit

A 2.5Gb/s clock and data recovery （CDR） circuit is designed and realized in TSMC＇s standard 0.18/μm CMOS process. The clock recovery is based on a PLL. For phase noise optimization,a dynamic phase and frequency detector （PFD） is used in the PLL. The rms jitter of the recovered 2.5GHz clock is 2.4ps and the SSB phase noise is - 111dBc/Hz at 10kHz offset. The rms jitter of the recovered 2.5Gb/s data is 3.3ps. The power consumption is 120mW.

2.5Gb/s Monolithic IC of Clock Recovery,Data Decision,and 1∶4 Demultiplexer

A high integrated monolithic IC, with functions of clock recovery, data decision, and 1 ： 4 demultiplexer,is implemented in 0.25μm CMOS process for 2.5Gb/s fiber-optic communications. The recovered and frequency divided 625MHz clock has a phase noise of -106.26dBc/Hz at 100kHz offset in response to a 2.5Gb/s PRBS input data （2^31-1）. The 2.5Gb/s PRBS data are demultiplexed to four 625Mb/s data. The 0.97mm× 0.97mm IC consumes 550mW under a single 3.3V power supply （not including output buffers）.

2.488 Gbit/s clock and data recovery circuit in 0.35 μm CMOS

The design of a 2. 488 Gbit/s clock and data recovery （CDR） If for synchronous digital hierarchy （SDH） STM-16 receiver is described. Based on the injected phase-locked loop （IPLL） and D-flip flop architectures, the CDR IC was implemented in a standard 0. 35 μan complementary metal-oxide-semiconductor （CMOS） technology. With 2^31 -1 pseudorandom bit sequences （PRBS） input, the sensitivity of data recovery circuit is less than 20 mV with 10^-12 bit error rate （BER）. The recovered clock shows a root mean square （rms） jitter of 2. 8 ps and a phase noise of - 110 dBc/Hz at 100 kHz offset. The capture range of the circuit is larger than 40 MHz. With a 5 V supply, the circuit consumes 680 mW and the chip area is 1.49 mm × 1 mm.

Analysis and Design of a Phase Interpolator for Clock and Data Recovery

In this paper,a detailed analysis of a phase interpolator for clock recovery is presented. A mathematical model is setup for the phase interpolator and we perform a precise analysis using this model. The result shows that the output amplitude and linearity of phase interpolator is primarily related to the difference between the two input phases. A new encoding pattern is given to solve this problem. Analysis in the circuit domain was also undertaken. The simulation results show that the relation between RC time-constant and time difference of input clocks affects the linearity of the phase interpolator. To alleviate this undesired effect, two adjustable-RC buffers are added at the input of the PI. Finally,a 90nm CMOS phase interpolator,which can work in the frequency from 1GHz to 5GHz,is proposed. The power dissipation of the phase interpolator is lmW with a 1.2V power supply. Experiment results show that the phase interpolator has a monotone output phase and good linearity.

A 2 .5Gb/s GaAs MESFET Clock Recovery and Decision Circuit

A 2 5Gb/s depletion mode GaAs MESFET clock recovery and decision circuit is described,which applies to the optical fiber communication.The circuit consists of a clock recovery circuit,including a preprocessor,phase detector(PD),low pass filter(LPF) and voltage controlled oscillator(VCO) and a decision circuit,including a comparator and a latch.The SPICE simulation result confirms the high frequency 2 5GHz of the clock recovery and the high speed 2 5Gb/s of the decision circuit.The 2 5Gb/s decision circuit has proved to be able to deal with the input signal and produce a digital output signal after it being sampled by a clock signal.

A 5-Gbit/s monolithically-integrated low-power clock recovery circuit in 0.18-μm CMOS

In order to make a 10 Gbit/s 2：1 half-rate multiplexer operate without external clocks, a 5 Gbit/s clock recovery （CR） circuit is needed to extract the desired clock from one input data. For the CR circuit, a 3-stage ring voltage-controlled oscillator （VCO） is employed to avoid an unreliable startup of a 2-stage VCO and a low oscillation frequency of a 4-stage VCO. A phase frequency detector （PFD） is used to expand the pull-in range to meet the wide tuning range of a VCO required by process-voltage-temperature （PVT） variation. SMIC 0. 18-μm CMOS technology is adopted and the core area is 170 μm ×270 μm. Measurements show that, under a 1.8 V supply voltage, it consumes only about 90 mW, and has an input sensitivity of less than 25 mV, an output single-ended swing of above 300 mV, a phase noise of - 114 dBc/Hz at 1 MHz offset and a pull-in range of 1 GHz.

Performance analysis of a novel chip tracking loop used for regenerative pseudo-noise ranging clock recovery

To improve the performance of composite pseudo-noise （PN） code clock recovery in a regenerative PN ranging system at a low symbol signal-to-noise ratio （SNR）, a novel chip tracking loop （CTL） used for regenerative PN ranging clock recovery is adopted. The CTL is a modified data transition tracking loop （DTTL）. The difference between them is that the Q channel output of the CTL is directly multiplied by a clock component, while that of the DTTL is multiplied by the Ⅰ channel transition detector output. Under the condition of a quasi-squareware PN ranging code, the tracking （ mean square timing jitter） performance of the CTL is analyzed. The tracking performances of the CTL and the DTTL, are compared over a wide range of symbol SNRs. The result shows that the CTL and the DTTL have the same performance at a large symbol SNR, while at a low symbol SNR, the former offers a noticeable enhancement.

Energy Recovery Threshold Logic and Power Clock Generation Circuits

Energy recovery threshold logic (ERTL) is proposed,which combines threshold logic with adiabatic approach.ERTL achieves low energy as well as low gate complexity.A high efficiency power clock generator is also proposed,which can adjust duty cycle of MOS switch in power clock generator depending on logic complexity and operating frequency to achieve optimum energy efficiency.Closed-form results are derived,which facilitate efficiency-optimized design of the power clock generator.An ERTL PLA and a conventional PLA are designed and simulated on 0.35μm process.The energy efficiency of the proposed power clock generator can reach 77%～85% operating between 20～100MHz.Simulation results indicate that ERTL is a low energy logic.Including power loss of power clock circuits,ERTL PLA still shows 65%～77% power savings compared to conventional PLA.

面向Duobinary信号的时钟恢复电路研究与设计

高速串行接口是高性能计算机系统中芯片之间的互连核心,针对高速串行通信所需高带宽问题,在Candence平台上基于Verilog-AMS完成56 Gbps Duobinary信号时钟数据恢复电路设计与仿真,多电平传输可以减小对带宽的需求。基于相位差值器(PI)设计时钟数据恢复(CDR)电路,以Bang-Bang鉴相器的鉴相结果作为鉴相依据,采用数字信号处理(DSP)算法处理鉴相结果,其包括投票算法、滤波算法以及相位控制码转换算法。数字算法降低了电路设计的复杂度,便于调节环路增益,提高了系统的稳定性,降低环路延迟。仿真结果表明,该CDR电路可以进行相差和100 PPM频差的追踪。对输入数据分别增加0.25 UI正弦抖动,环路带宽为23 MHz,当抖动频率未超过环路带宽时,系统能够跟踪正弦抖动。抖动容限满足CEI-56G协议规范。

应用于0.5~12.5Gb/s CMOS时钟数据恢复电路的相位插值器设计

文中采用28 nm CMOS工艺,设计了一款应用于半速率CDR电路中的相位插值器。该插值器采用锁相环提供的正交参考时钟,通过编码控制的DAC电流源调整电流权重控制输出相位,一个周期内可实现128次相位插值。为了提高接收器在多通道、多协议的性能,提出了输入时钟整形电路对斜率进行调节,提高了线性度。仿真结果表明,插值器在6.25 GHz工作频率下线性度良好,微分非线性(DNL)最大不超过1 LSB,积分非线性(INL)最大不超过2 LSB,实现了高线性度、宽频率范围的设计目标。

基于不同模糊度固定产品的PPP-AR定位性能评估

基于CODE、GFZ、CNES、武汉大学PRIDE实验室和内部估计的模糊度固定产品,从收敛时间、首次固定时间及定位精度等方面进行PPP-AR固定性能的研究。实验选用2022年40个IGS测站7 d的观测数据和各模糊度固定产品配套使用的精密产品,结果表明,在置信度为95%的静态解算模式下,5种产品在解算时间为1 h时固定解较浮点解定位精度提升最明显,分别提升46.58%(3.4 cm)、41.10%(3.0 cm)、45.21%(3.3 cm)、34.25%(2.5 cm)和41.10%(3.0 cm)。仿动态解算模式下,5种产品E、N方向的定位精度都能达到mm级,U方向较浮点解精度提升较小,其中使用GBM产品的精度提升最小,E、N、U方向分别提高72.73%(2.4 cm)、47.37%(0.9 cm)、5.41%(0.2 cm);提升效果较好的是WUM和COM产品,分别为81.82%(2.7 cm)、63.16%(1.2 cm)、24.32%(1.1 cm)和81.82%(2.7 cm)、63.16%(1.2 cm)、15.58%(0.8 cm)。

一种集成DFE和CDR的56 Gbit/s PAM-4 SerDes接收机设计

基于65 nm CMOS工艺设计了一款1/4速率56 Gbit/s PAM-4 SerDes接收机,该接收机集成了可变增益放大、连续时间线性均衡(CTLE)、判决反馈均衡(DFE)、自适应阈值电压跟踪和无参考时钟数据恢复(CDR)等电路。可变增益放大技术被用来对接收信号进行幅度调节;CTLE和2抽头DFE被用来进行信道畸变补偿;自适应阈值电压跟踪技术用来确定最优的PAM-4信号判决电平;无参考时钟CDR技术则在无外部参考时钟的前提下,被用来产生最佳判决时钟,同时基于边沿检测技术有效降低了PAM-4信号非对称电平转换引起的时钟抖动。后仿真结果表明,在1.2 V电源电压下,所设计的PAM-4接收机能够实现6.75~20.75 dB的可调增益范围和高达16 dB@14 GHz的信道高频衰减补偿,且在16.1 dB@14 GHz信道下,CDR提取出的7 GHz时钟抖动峰峰值为7.21 ps。工作于56 Gbit/s速率下,接收机功耗为227 mW,能效为4.05 pJ/bit。

A 28/56 Gb/s NRZ/PAM-4 dual-mode transceiver with 1/4 rate reconfigurable 4-tap FFE and half-rate slicer in a 28-nm CMOS

A 28/56 Gb/s NRZ/PAM-4 dual-mode transceiver(TRx)designed in a 28-nm complementary metal-oxide-semiconduc-tor(CMOS)process is presented in this article.A voltage-mode(VM)driver featuring a 4-tap reconfigurable feed-forward equal-izer(FFE)is employed in the quarter-rate transmitter(TX).The half-rate receiver(RX)incorporates a continuous-time linear equal-izer(CTLE),a 3-stage high-speed slicer with multi-clock-phase sampling,and a clock and data recovery(CDR).The experimen-tal results show that the TRx operates at a maximum speed of 56 Gb/s with chip-on board(COB)assembly.The 28 Gb/s NRZ eye diagram shows a far-end vertical eye opening of 210 mV with an output amplitude of 351 mV single-ended and the 56 Gb/s PAM-4 eye diagram exhibits far-end eye opening of 33 mV(upper-eye),31 mV(mid-eye),and 28 mV(lower-eye)with an output amplitude of 353 mV single-ended.The recovered 14 GHz clock from the RX exhibits random jitter(RJ)of 469 fs and deterministic jitter(DJ)of 8.76 ps.The 875 Mb/s de-multiplexed data features 593 ps horizontal eye opening with 32.02 ps RJ,at bit-error rate(BER)of 10-5(0.53 UI).The power dissipation of TX and RX are 125 and 181.4 mW,respectively,from a 0.9-V sup-ply.

基于联合时钟恢复和均衡技术的光互连信号处理方法

在数据中心光互连系统中,针对时钟恢复模块和均衡模块相互依赖而导致两模块先决条件冲突的问题,提出了联合均衡和定时恢复反馈环路的数字信号处理方案。该方案针对PAM4信号特征,采用了改进的Gardner反馈式全数字时钟同步算法,以降低时钟恢复误差、提高收敛性能;在均衡模块,提出并采用了一种基于T/2分数间隔的改进级联多模盲均衡算法,以减小均衡稳态误差、改善信号均衡效果。仿真结果表明,该联合方案能够降低系统误码率,在满足硬判决前向纠错阈值下,40 km传输后的接收机灵敏度为-16 dBm,相较于级联方案提升了至少3 dBm。同时,联合方式的抗抽样时钟偏移(SCO)的能力更强,最大能容忍的SCO提高约200个时钟偏移量,说明本方案可以有效补偿线性损伤和时钟误差。

高兼容性亚码元级激光通信/测距一体化系统

随着全社会的数字化转型,空天地一体化信息网络被迅速布局,对卫星间的多调制格式的高速相干光通信和高精度测距的需求愈加迫切。基于相干光通信,提出了一种低成本、低复杂度、高精度的通信/测距一体化系统,通过在相干光通信系统中间隔插入特定的测距数据帧,并利用改进的并行数字时钟恢复(CDR)算法,由其中的鉴相模块提取相位偏差信息,无需消耗额外的硬件资源即可实现高精度测距,由此满足卫星上低功耗、低重量和小尺寸的需求。此外,该系统可兼容不同相干光调制格式,包括OOK、BPSK和QPSK以及不同传输速率的相干光通信链路,体现出了高兼容性。提出的系统在现场可编程门阵列(FPGA)上进行实验验证,在625 Mbps和1 Gbps的BPSK信号下进行通信/测距实验。实验结果表明,码元持续时间为1.6 ns和1 ns,测距精度达到码元时长的2.25%和4.74%,测距精度分别为11 mm和14 mm,达到亚码元量级。通过所提出的通信/测距一体化系统,解决了现有测距系统通用性较差,复杂度较高的问题,提升了系统的灵活性。

时频域结合的量子通信时间同步方法

时间同步对于星地量子密钥分发至关重要。以往的方案中为了在噪声干扰较大、信号丢失严重的星地链路中完成量子光同步,需要全球定位系统(GPS)信号辅助同步光来完成。为了降低系统的复杂性和成本,本文提出了一种时域与频域相结合的时间同步方法。该方法利用量子光序列的频谱特性以及线性拟合方法,实现了高精度的时间同步。对于星地量子密钥分发的实验数据进行测试,可以实现1.03 ns的同步精度,直方图半高宽为1.4 ns。该方法不需要使用GPS以及同步光,可以广泛地应用于星地量子密钥分发。