Progress on Transition Metal Ions Dissolution Suppression Strategies in Prussian Blue Analogs for Aqueous Sodium-/Potassium-Ion Batteries

Aqueous sodium-ion batteries(ASIBs)and aqueous potassium-ion batteries(APIBs)present significant potential for large-scale energy storage due to their cost-effectiveness,safety,and environmental compatibility.Nonetheless,the intricate energy storage mechanisms in aqueous electrolytes place stringent require-ments on the host materials.Prussian blue analogs(PBAs),with their open three-dimensional framework and facile synthesis,stand out as leading candidates for aqueous energy storage.However,PBAs possess a swift capacity fade and limited cycle longevity,for their structural integrity is compromised by the pronounced dis-solution of transition metal(TM)ions in the aqueous milieu.This manuscript provides an exhaustive review of the recent advancements concerning PBAs in ASIBs and APIBs.The dissolution mechanisms of TM ions in PBAs,informed by their structural attributes and redox processes,are thoroughly examined.Moreover,this study delves into innovative design tactics to alleviate the dissolution issue of TM ions.In conclusion,the paper consolidates various strategies for suppressing the dissolution of TM ions in PBAs and posits avenues for prospective exploration of high-safety aqueous sodium-/potassium-ion batteries.

Experimental and computational optimization of Prussian blue analogues as high-performance cathodes for sodium-ion batteries:A review

In this review,we discuss the electrochemical properties of Prussian blue(PB)for Na^(+)storage by combining structural engineering and electrolyte modifications.We integrated experimental data and density functional theory(DFT)in sodium-ion battery(SIB)research to refine the atomic arrangements and crystal lattices and introduce substitutions and dopants.These changes affect the lattice stability,intercalation,electronic and ionic conductivities,and electrochemical performance.We unraveled the intricate structure-electrochemical behavior relationship by combining experimental data with computational models,including first-principles calculations.This holistic approach identified techniques for optimizing PB and Prussian blue analog(PBA)structu ral properties for SIBs.We also discuss the tuning of electrolytes by systematically adjusting their composition,concentration,and additives using a combination of molecular dynamics(MD)simulations and DFT computations.Our review offers a comprehensive assessment of strategies for enhancing the electrochemical properties of PB and PBAs through structural engineering and electrolyte modifications,combining experimental insights with advanced computational simulations,and paving the way for next-generation energy storage systems.

An Adaptive Control Strategy for Energy Storage Interface Converter Based on Analogous Virtual Synchronous Generator

In the DC microgrid,the lack of inertia and damping in power electronic converters results in poor stability of DC bus voltage and low inertia of the DC microgrid during fluctuations in load and photovoltaic power.To address this issue,the application of a virtual synchronous generator(VSG)in grid-connected inverters control is referenced and proposes a control strategy called the analogous virtual synchronous generator(AVSG)control strategy for the interface DC/DC converter of the battery in the microgrid.Besides,a flexible parameter adaptive control method is introduced to further enhance the inertial behavior of the AVSG control.Firstly,a theoretical analysis is conducted on the various components of the DC microgrid,the structure of analogous virtual synchronous generator,and the control structure’s main parameters related to the DC microgrid’s inertial behavior.Secondly,the voltage change rate tracking coefficient is introduced to adjust the change of the virtual capacitance and damping coefficient flexibility,which further strengthens the inertia trend of the DC microgrid.Additionally,a small-signal modeling approach is used to analyze the approximate range of the AVSG’s main parameters ensuring system stability.Finally,conduct a simulation analysis by building the model of the DC microgrid system with photovoltaic(PV)and battery energy storage(BES)in MATLAB/Simulink.Simulation results from different scenarios have verified that the AVSG control introduces fixed inertia and damping into the droop control of the battery,resulting in a certain level of inertia enhancement.Furthermore,the additional adaptive control strategy built upon the AVSG control provides better and flexible inertial support for the DC microgrid,further enhances the stability of the DC bus voltage,and has a more positive impact on the battery performance.

A Low-Power 12-Bit SAR ADC for Analog Convolutional Kernel of Mixed-Signal CNN Accelerator

As deep learning techniques such as Convolutional Neural Networks(CNNs)are widely adopted,the complexity of CNNs is rapidly increasing due to the growing demand for CNN accelerator system-on-chip(SoC).Although conventional CNN accelerators can reduce the computational time of learning and inference tasks,they tend to occupy large chip areas due to many multiply-and-accumulate(MAC)operators when implemented in complex digital circuits,incurring excessive power consumption.To overcome these drawbacks,this work implements an analog convolutional filter consisting of an analog multiply-and-accumulate arithmetic circuit along with an analog-to-digital converter(ADC).This paper introduces the architecture of an analog convolutional kernel comprised of low-power ultra-small circuits for neural network accelerator chips.ADC is an essential component of the analog convolutional kernel used to convert the analog convolutional result to digital values to be stored in memory.This work presents the implementation of a highly low-power and area-efficient 12-bit Successive Approximation Register(SAR)ADC.Unlink most other SAR-ADCs with differential structure;the proposed ADC employs a single-ended capacitor array to support the preceding single-ended max-pooling circuit along with minimal power consumption.The SARADCimplementation also introduces a unique circuit that reduces kick-back noise to increase performance.It was implemented in a test chip using a 55 nm CMOS process.It demonstrates that the proposed ADC reduces Kick-back noise by 40%and consequently improves the ADC’s resolution by about 10%while providing a near rail-to-rail dynamic rangewith significantly lower power consumption than conventional ADCs.The ADC test chip shows a chip size of 4600μm^(2)with a power consumption of 6.6μW while providing an signal-to-noise-and-distortion ratio(SNDR)of 68.45 dB,corresponding to an effective number of bits(ENOB)of 11.07 bits.

High-Bandwidth,Low-Power CMOS Transistor Based CAB for Field Programmable Analog Array

This article presents an integrated current mode configurable analog block(CAB)system for field-programmable analog array(FPAA).The proposed architecture is based on the complementary metal-oxide semiconductor(CMOS)transistor level design where MOSFET transistors operating in the saturation region are adopted.The proposed CAB architecture is designed to implement six of thewidely used current mode operations in analog processing systems:addition,subtraction,integration,multiplication,division,and pass operation.The functionality of the proposed CAB is demonstrated through these six operations,where each operation is chosen based on the user’s selection in the CAB interface system.The architecture of the CAB system proposes an optimized way of designing and integrating only three functional cells with the interface circuitry to achieve the six operations.Furthermore,optimized programming and digital tuning circuitry are implemented in the architecture to control and interface with the functional cells.Moreover,these designed programming and tuning circuitries play an essential role in optimizing the performance of the proposed design.Simulation of the proposed CMOS Transistor Based CAB system is carried out using Tanner EDA Tools in 0.35μm standard CMOS technology.The design uses a±1.5 V power supply and results in maximum 3 dB bandwidth of 34.9 MHz and an approximate size of 0.0537 mm2.This demonstrates the advantages of the design over the current state-of-the-art designs presented for comparison in this article.Consequently,the proposed design has a clear aspect of simplicity,low power consumption,and high bandwidth operation,which makes it a suitable candidate for mobile telecommunications applications.

Structural Variation between the Western and Eastern Kuqa Fold-and-thrust Belt,China:Insights from Seismic Interpretation and Analog Modeling

The Kuqa fold-and-thrust belt exhibits apparent structural variation in the western and eastern zone.Two salt layer act as effective decollements and influence the varied deformation.In this study,detailed seismic interpretations and analog modeling are presented to construct the suprasalt and subsalt structures in the transfer zone of the middle Kuqa and investigate the influence of the two salt layers.The results reveal that the relationship of the two salt layers changes from separated to connected,and then overlapped toward the foreland in the transfer zone.Different structural models are formed in the suprasalt and subsalt units due to the interaction of the two salt layers.The imbricate thrust faults form two broom-like fault systems in the subsalt units.The suprasalt units develop detached folds terminating toward the east in the region near the orogenic belt.Whereas,two offset anticlines with different trends develop at the frontal edge of the lower salt layer and the trailing edge of the upper salt layer,respectively.According to exploration results in this region,the relationship between suprasalt and subsalt structures has an influence on hydrocarbon accumulation.We believe that the connected deformation contains high-risk plays while the decoupled deformation contains well-preserved plays.

Performance optimization of tri-gate junctionless FinFET using channel stack engineering for digital and analog/RF design

This manuscript explores the behavior of a junctionless tri-gate FinFET at the nano-scale region using SiGe material for the channel.For the analysis,three different channel structures are used:(a)tri-layer stack channel(TLSC)(Si-SiGe-Si),(b)double layer stack channel(DLSC)(SiGe-Si),(c)single layer channel(SLC)(S_(i)).The I−V characteristics,subthreshold swing(SS),drain-induced barrier lowering(DIBL),threshold voltage(V_(t)),drain current(ION),OFF current(IOFF),and ON-OFF current ratio(ION/IOFF)are observed for the structures at a 20 nm gate length.It is seen that TLSC provides 21.3%and 14.3%more ON current than DLSC and SLC,respectively.The paper also explores the analog and RF factors such as input transconductance(g_(m)),output transconductance(gds),gain(gm/gds),transconductance generation factor(TGF),cut-off frequency(f_(T)),maximum oscillation frequency(f_(max)),gain frequency product(GFP)and linearity performance parameters such as second and third-order harmonics(g_(m2),g_(m3)),voltage intercept points(VIP_(2),VIP_(3))and 1-dB compression points for the three structures.The results show that the TLSC has a high analog performance due to more gm and provides 16.3%,48.4%more gain than SLC and DLSC,respectively and it also provides better linearity.All the results are obtained using the VisualTCAD tool.

Dynamic Analogical Association Algorithm Based on Manifold Matching for Few-Shot Learning

At present,deep learning has been well applied in many fields.However,due to the high complexity of hypothesis space,numerous training samples are usually required to ensure the reliability of minimizing experience risk.Therefore,training a classifier with a small number of training examples is a challenging task.From a biological point of view,based on the assumption that rich prior knowledge and analogical association should enable human beings to quickly distinguish novel things from a few or even one example,we proposed a dynamic analogical association algorithm to make the model use only a few labeled samples for classification.To be specific,the algorithm search for knowledge structures similar to existing tasks in prior knowledge based on manifold matching,and combine sampling distributions to generate offsets instead of two sample points,thereby ensuring high confidence and significant contribution to the classification.The comparative results on two common benchmark datasets substantiate the superiority of the proposed method compared to existing data generation approaches for few-shot learning,and the effectiveness of the algorithm has been proved through ablation experiments.

A 5MS/s 12-Bit Successive Approximation Analog-to-Digital Converter

With the continuous development of science and technology, digital signal processing is more and more widely used in various fields. Among them, the analog-to-digital converter (ADC) is one of the key components to convert analog signals to digital signals. As a common type of ADC, 12-bit sequential approximation analog-to-digital converter (SAR ADC) has attracted extensive attention for its performance and application. This paper aims to conduct in-depth research and analysis of 12-bit SAR ADC to meet the growing demands of digital signal processing. This article designs a 12-bit, successive approximation analog-to-digital converter (SAR ADC) with a sampling rate of 5 MS/s. The overall circuit adopts a fully differential structure, with key modules including DAC capacitor array, comparator, and control logic. According to the DAC circuit in this paper, a fully differential capacitor DAC array structure is proposed to reduce the area of layout DAC. The comparator uses a digital dynamic comparator to improve the ADC conversion speed. The chip is designed based on the SMIC180 nm CMOS process. The simulation results show that when the sampling rate is 5 MS/s, the effective bit of SAR ADC is 11.92 bit, the SNR is 74.62 dB, and the SFDR is 89.24 dB.

基于Analog Discovery 2的巨磁阻效应实验系统

将口袋式仪表Analog Discovery 2及其配套控制软件WaveForms引入巨磁阻效应实验,替代直流电源、信号发生器、示波器、数字信号控制器等传统仪表,完成信号的激发、采集以及处理.由Analog Discovery 2驱动螺线管、巨磁阻传感器、直流电机和步进电机等部件,可以实现巨磁阻传感器R-B基本特征曲线和高速转动转速的快速测量,还可以结合齿轮状铁磁体,实现低速转动的准确测量及微小角位移的定标和测量.各主要部件采用三维调整架固定,偏置永磁铁也配备了不同形状的导磁头,方便学生观察不同条件下的实验现象,完成更具有开放性和创新性的实验内容.

Treatment of central precocious puberty by GnRH analogs： long-term outcome in men

In boys, central precocious puberty （CPP） is the appearance of secondary sex characteristics driven by pituitary gonadotropin secretion before the age of 9 years. In the last years, relevant improvements in the treatment of CPP have been achieved. Because CPP is rare in boys, the majority of papers on this issue focus on girls and do not address specific features of male patients regarding end results and safety. In the present paper, recent advances of CPP management with GnRH analogs in men are summarized. End results in untreated and treated patients are also reviewed by an analysis of the recently published literature on treatment of CPP in men. The available data indicate that therapy with GnRH analogs can improve final height into the range of target height without significant adverse short-term and long-term effects, but longer follow-up of larger series of patients is still required to draw definitive conclusions.

电子细胞模型Analog-Cell中前体mRNA剪接过程的模拟与研究

真核细胞前体mRNA的剪接加工包含内含子剪切和外显子拼接两个过程,是真核细胞基因表达过程中的一个重要环节.针对这一环节,提出了一种模拟真核细胞前体mRNA内含子剪切及其选择性剪接的算法,并在自主研发的电子细胞模型Analog-Cell中实现了该算法,且获得了符合生物学原理的模拟结果.模拟结果表明,该算法可使剪接体高效、准确地模拟内含子的剪接过程,并形成套索结构,同时有选择地将外显子片段拼接起来,最终形成成熟的mRNA.

复杂企业网服务器端Analogy Factory设计模式

利用servlet良好的可扩展性 ,提出一种全新的Web服务器端设计模式———AnalogyFactory模式 ,将企业的业务逻辑从servlet中剥离 ,以独立的接口继承体系实现 ,并用动态加载方式获得其实例 ,可以在不重新编译服务器端控制逻辑的前提下更新功能 ,甚至加入新模块 ,从而适应企业复杂多变的网络环境和应用需求 .本设计模式运用于实际系统的开发 ,较好地解决了复杂网络的网络拥塞。

Overview of Energy-Efficient Successive-Approximation Analog-to-Digital Converters: State-of-the-Art and a Design Example

This paper makes a review of state-of-the- arts designs of successive-approximation register analog-to-digital converters （SAR ADCs）. Methods and technique specifications are collected in view of innovative ideas. At the end of this paper, a design example is given to illustrate the procedure to design an SAR ADC. A new method, which extends the width of the internal clock, is also proposed to facilitate different sampling frequencies, which provides more time for the digital-to-analog convert （DAC） and comparator to settle. The 10 bit ADC is simulated in 0.13 μm CMOS process technology. The signal-to-noise and distortion ratio （SNDR） is 54.41 dB at a 10 MHz input with a 50 MS/s sampling rate, and the power is 330 μW.

Forecasting the Quasi-stationary Front Rainstorm in Southeast China Using the Synthetically Multilevel Analog Forecast Technology

The authors use numerical model integral products in a third level forecast of synthetically multi-level analog forecast technology.This is one of the strongest points of this study,which also includes the re-ducing mean vacant-forecast rate method,which pos-sesses many advantages with regard to filtering the analog term.Moreover,the similitude degree between samples is assessed using a combination of meteorological elements,which works better than that described using a single element in earlier analog forecast studies.Based on these techniques,the authors apply the model output,air sounding,surface observation and weather map data from 1990 to 2002 to perform an analog experiment of the quasi-stationary front rainstorm.The most important re-sults are as follows:(1) The forecast successful index is 0.36,and was improved after the forecast model was re-vised.(2) The forecast precise rate (0.59) and the lost-forecast rate (0.33) are also better than those of other methods.(3) Based on the model output data,the syn-thetically multilevel analog forecast technology can pro-duce more accurate forecasts of a quasi-stationary front rainstorm.(4) Optimal analog elements reveal that trig-gering mechanisms are located in the lower troposphere while upper level systems are more important in main-taining the phase of the rainstorm.These variables should be first taken into account in operational forecasts of the quasi-stationary front rainstorm.(5) In addition,experi-ments reveal that the position of the key zone is mainly decided by the position of the system causing the heavy rainfall.

MIXED-GRAINED CMOS FIELD PROGRAMMABLE ANALOG ARRAY FOR SMART SENSORY APPLICATIONS

The drive towards shorter design cycles for analog integrated circuits has given impetus to the development of Field Programmable Analog Arrays(FPAAs),which are the analogue counterparts of Field Programmable Gate Arrays(FPGAs).In this paper,we present a new design methodology which using FPAA as a powerful analog front-end processing platform in the smart sensory microsystem.The proposed FPAA contains 16 homogeneous mixed-grained Configurable Analog Blocks(CABs) which house a variety of processing elements especially the proposed fine-grained Core Configurable Amplifiers(CCAs).The high flexible CABs allow the FPAA operating in both continuous-time and discrete-time approaches suitable to support variety of sensors.To reduce the nonideal parasitic effects and save area,the fat-tree interconnection network is adopted in this FPAA.The functionality of this FPAA is demonstrated through embedding of voltage and capacitive sensor signal readout circuits and a configurable band pass filter.The minimal detectable voltage and capacitor achieves 38 uV and 8.3 aF respectively within 100 Hz sensor bandwidth.The power consumption comparison of CCA in three applications shows that the FPAA has high power efficiency.And the simulation results also show that the FPAA has good tolerance with wide PVT variations.

Adaptive micro-extended-analog-computer array with a linear Lukasiewicz function

A micro-extended-analog-computer （uEAC） is developed on the basis of Rubel＇ s extended analog computer（EAC） model. Through the uEAC mathematical model, the resistance properties of the conductive sheet, several feedback uEAC models, and a more flexible uEAC cell structure with a multi-level hierarchy are discussed. Futhermore, for the dynamic uEAC array with a linear Lukasiewicz function, a nonlinear differential equation description is presented, and then a sufficient global asymptotic stability condition is derived by utilizing a Lyapunov function and a Lipchitz function. Finally, comparative simulations for a cam servo mechanism system are conducted to verify the capability of the uEAC array as an adaptive controller.

The Cognitive Function of Analogical Inference and Its Effect on Innovation

As a method of logical thinking,analogical inference has a long history both in ancient Greece and in the ancient East,and has been widely used in the daily life.Even today it still plays an important role in understanding and improving the world.Particularly,its cognitive function is not only reflected in the interpretation and further understanding of the existing knowledge,but more importantly,it can still improve our scientific level,expand our cognitive field,and help us open up the unknown field.That,of course,is where its innovation lies.From the perspective of analogical inference,its innovative function should be based on the identical or at least the similar relationship between the things.In addition,it should also be based on the ability of imagination played by the cognition subject.

Analog-to-digital conversion of information in the retina

We considered the physiological mechanisms of functioning of the retina’s neural network. It is marked that the primary function of a neural network is an analog-to-digital conversion of the receptor potential of photoreceptor into the pulse-to-digital signal to ganglion cells. We showed the role of different types of neurons in the work of analog-to-digital converter. We gave the equivalent circuit of this converter. We researched the mechanism of the numeric coding of the receptor potential of the photoreceptor.

Canonic Realizations of Voltage-Controlled Floating Inductors Using CFOAs and Analog Multipliers

New voltage-controlled floating inductors employing CFOAs and an analog multiplier have been presented which have the attractive features of using a canonic number of passive components (only two resistors and a capacitor) and not requiring any component-matching conditions and design constraints for the intended type of inductance realization. The workability and applications of the new circuits have been demonstrated by SPICE simulation and hardware experimental results based upon AD844-type CFOAs and AD633-type/MPY534 type analog multipliers.