A 5MS/s 12-Bit Successive Approximation Analog-to-Digital Converter

With the continuous development of science and technology, digital signal processing is more and more widely used in various fields. Among them, the analog-to-digital converter (ADC) is one of the key components to convert analog signals to digital signals. As a common type of ADC, 12-bit sequential approximation analog-to-digital converter (SAR ADC) has attracted extensive attention for its performance and application. This paper aims to conduct in-depth research and analysis of 12-bit SAR ADC to meet the growing demands of digital signal processing. This article designs a 12-bit, successive approximation analog-to-digital converter (SAR ADC) with a sampling rate of 5 MS/s. The overall circuit adopts a fully differential structure, with key modules including DAC capacitor array, comparator, and control logic. According to the DAC circuit in this paper, a fully differential capacitor DAC array structure is proposed to reduce the area of layout DAC. The comparator uses a digital dynamic comparator to improve the ADC conversion speed. The chip is designed based on the SMIC180 nm CMOS process. The simulation results show that when the sampling rate is 5 MS/s, the effective bit of SAR ADC is 11.92 bit, the SNR is 74.62 dB, and the SFDR is 89.24 dB.

Effect of ionizing radiation on dual 8-bit analog-to-digital converters (AD9058) with various dose rates and bias conditions

The radiation effects on several properties （reference voltage, digital output logic voltage, and supply current） of dual 8-bit analog-to-digital （A/D） converters （AD9058） under various biased conditions are investigated in this paper. Gamma ray and 10-MeV proton irradiation are selected for a detailed evaluation and comparison. Based on the measurement results induced by the gamma ray with various dose rates, the devices exhibit enhanced low dose rate sensitivity （ELDRS） under zero and working bias conditions. Meanwhile, it is obvious that the ELDRS is more severe under the working bias condition than under the zero bias condition. The degradation of AD9058 does not display obvious ELDRS during 10-MeV proton irradiation with the selected flux.

Design of Digital to Analog Converters with Arbitrary Radix

There are DAC structures available in the literature for radix r = 2, 3, and 4;but how they are arrived at is missing. No general structure is available for any radix r. The aim of the paper is, therefore, to fulfil these gaps. To start with, the design relations are derived for the simplest possible attenuator circuit when connected to a voltage source V and a series resistance R, such that the complete circuit offers the Thevenin resistance R. Spread relations for this attenuator are derived. An example when 3 such attenuators with different attenuation constants are connected in cascade is given. Interestingly, the two attenuators with attenuation factors 1/2 and 1/3 have the same spread of 2. A generalized attenuator is then obtained when N number of identical attenuators are connected in cascade. This is modified to derive a digital to analog converter for any radix r.

一种应用于12 bit SAR ADC C-R混和式DAC

针对ADC中功耗、精度与成本之间相互制约的问题,提出一种应用于12 bitSARADC的混合电容电阻型(C-R)DAC结构。高6位采用温度计编码的电容阵列结构;低6位选择电阻阵列结构。对电路进行非线性分析选取合理的元件尺寸。另外,采用非交叠时钟电路作为开关控制时序,避免开关切换时引起瞬态毛刺导致电容电荷泄露。基于GSMC 95 nm工艺,完成电路、版图设计与仿真,并完成流片测试,DAC版图总面积为317.2μm×262.5μm,流片测试结果表明,DNL的范围为-0.38~+0.44 LSB,INL的范围为-0.73~+0.4 LSB,满足12位ADC的设计要求。

一种基于冗余位结构CDAC的12 bit SAR ADC

提出一种基于非二进制冗余位结构CDAC的12 bit全差分逐次逼近型模拟数字转换器(SAR ADC)。传统SAR ADC中CDAC的单位电容数量随位数指数增长,且采用全差分结构的电容数量是单端结构的两倍,导致CDAC建立时间过长。为此,设计一种加入冗余位的分段式电容阵列,减少单位电容数量,提高CDAC建立速度。动态比较器的比较速度快,会导致数字码误判,通过加入冗余位弥补比较器对数字码误判的缺陷;采用底板采样技术,避免沟道电荷注入和时钟馈通,提高采样精度;采用SMIC 130 nm CMOS工艺。在电源电压1.2 V、20 MS/s采样率下,对1024点FFT仿真。结果显示:当输入频率(9.824 MHz)接近奈奎斯特频率时,该ADC的整体信噪失真比(SNDR)达到72.42 dB,有效位数(ENOB)达到11.73 bit;无杂散动态范围(SFDR)达到88.4 dBc,功耗为1.29 mW。

一种16位110 dB无杂散动态范围的低功耗SAR ADC

该文设计了一款16位、转换速率为625 kS/s的逐次逼近寄存器型模数转换器(SAR ADC)。改进的采样保持电路结构,优化了采样线性度和噪声性能。采用分段结构设计电容型数模转换器并使用混合方式的电容切换方案,减小面积和能耗。利用扰动注入技术提升ADC的线性度。比较器采用两级积分型预放大器减小噪声,利用输出失调存储技术及优化的电路设计减小了比较器失调电压和失调校准引入的噪声,优化并提升了比较器速度。芯片采用CMOS 0.18μm工艺设计和流片,ADC核心面积为1.15 mm^(2)。测试结果表明,在1 kHz正弦信号输入下,ADC差分输入峰峰值幅度达8.8 V,信纳比为85.9 dB,无杂散动态范围为110 dB,微分非线性为-0.27/+0.32 LSB,积分非线性为-0.58/+0.53 LSB,功耗为4.31 mW。

一种6倍无源增益低OSR低功耗的二阶NS SAR ADC

针对一阶噪声整形(NS)往往需要增加功耗而以较高的过采样比(OSR)来实现较高的有效位数(ENOB),提出了一种低OSR、低功耗的二阶无源NS SAR ADC。该无源NS模块较高的无源增益可以更好地抑制比较器的噪声;其残差电压是通过开关MOS阵列复用积分电容实现采样,从而无需额外的残差采样电容,避免了残差采样电容清零和残差采样时kT/C噪声的产生,因此减小了总的kT/C噪声。180 nm CMOS工艺仿真结果表明,在不使用数字校准的情况下,所设计的10位二阶无源NS SAR ADC电路以100 kS/s的采样率和5的OSR,实现了13.5位ENOB,电路功耗仅为6.98μW。

Simulation and Design Optimization of Novel Microelectromechanical Digital-to-Analog Converter

A microelectromechanical Digital to Analog Converter (DAC) based on Weighted Gap (WG) principle is described,which is analogous to the weighed resistor DAC in electronic circuits.To convert the input of binary voltage to the output of analog displacement,the gaps are proposed to be employed as a scale factor.A finite element method is used to simulate the performance of the DAC.To reduce the error,the structure design is optimized and the maximum error of 0 002μm is obtained.

基于高速ADC的数字双混频时差测量系统

使用双混频时差法进行时间和频率测量时,模拟部分引入的噪声会干扰信号过零点的判断,降低测量精度,而使用数字信号处理技术后不再需要判断过零点,量化噪声成为系统内的主要噪声来源,可以通过数字滤波器对其进行抑制。同时有利于设计结构紧凑的系统,更易于小型化,测量速度也可以进行灵活配置。通过引入高速模数转换器、数控振荡器、低通抽取滤波器、数字鉴相器等,设计了数字双混频时差测量系统,并研制了4通道的原理样机。测试结果表明,当频率源为10 MHz的信号时,原理样机中属于同片ADC(analog-to-digital converter)的两个通道间的本底噪声约为5×10^(-14)@1 s,属于不同片ADC的两个通道间的本底噪声约为8×10^(-14)@1 s,满足原子振荡器的测量要求。并以主动型氢钟VCH-1003M为参考,使用原理样机分别对Microchip的5071A铯原子钟和SRS的FS725铷原子钟的稳定度进行测量,测量结果与Microchip的相噪分析仪53100A和5120A无显著差异。

Energy-Efficient Large-Scale Antenna Systems with Hybrid Digital-Analog Beamforming Structure

A largescale antenna system （LSAS） with digital beamforming is expected to significantly increase energy efficiency （EE） and spectral efficiency （SE） in a wireless communication system. However, there are many challenging issues related to calibration, energy consumption, and cost in implementing a digital beamforming structure in an LSAS. In a practical LSAS deployment, hybrid digitalanalog beamforming structures with active antennas can be used. In this paper, we investigate the optimal antenna configuration in an N ＆#215; M beamforming structure, where N is the number of transceivers, M is the number of active antennas per transceiver, where analog beamforming is introduced for individual transceivers and digital beamforming is introduced across all N transceivers. We analyze the green point, which is the point of maximum EE on the EESE curve, and show that the logscale EE scales linearly with SE along a slope of lg2/N. We investigate the effect of M on EE for a given SE value in the case of fixed NM and independent N and M. In both cases, there is a unique optimal M that results in optimal EE. In the case of independent N and M, there is no optimal （N, M） combination for optimizing EE. The results of numerical simulations are provided, and these results support our analysis.

高精度低功耗噪声整形SAR ADC设计

针对传统无源有损积分环路滤波器相较于有源无损积分环路滤波器,具有功耗低、电路设计简单等特点,但其噪声传输函数(NTF:Noise Transfer Function)平滑,噪声整形效果较弱的问题,提出了一种无源无损的二阶积分环路滤波器,保留了无源有损积分优点的同时具有良好噪声整形效果。设计了一款分辨率为16 bit、采样率为2 Ms/s的混合架构噪声整形SAR ADC。仿真结果表明,在125 kHz带宽、过采样比为8时,实现了高信号与噪声失真比(SNDR(Signal to Noise and Distortion Ratio)为91.1 dB)、高精度(14.84 bit)和低功耗(285μW)的性能。

单极性ADC静态参数的测试方法

模数转换器(ADC)的静态指标包括微分非线性(DNL)和积分非线性(INL),测量静态参数的主要方法为码密度直方图法。传统的码密度直方图法对输入正弦波的幅值的计算精度有较高的要求,提出了一种基于码密度直方图的归一化处理的平台方案。根据测试要求,选取符合要求的测试激励幅值输入,从而对归一化处理后的方案有效性进行验证。实验结果表明进行归一化处理降低了正弦波幅值的变化对于码密度直方图法的影响,提高了码密度直方图法测试的稳定性。

一种具有1~128倍可变增益放大器的低功耗Sigma⁃Delta ADC

为满足传感器应用的低功耗需求,设计并实现了一种低功耗Sigma⁃Delta模数转换器(ADC)芯片。该ADC采用一阶全差分开关电容Sigma⁃Delta调制器,且集成了可编程增益放大器(PGA)和Bandgap;使用1.5 bit量化结构,相较于1 bit量化结构减小了3 dB的量化误差;使用优化的反馈电路,减小了电容失配引入的误差;PGA采用轨到轨的运放电路拓扑,增大了整个芯片的电压适应范围。基于180 nm CMOS工艺对该ADC进行了设计和流片。测试结果表明:该Sigma⁃Delta ADC在采样频率512 kHz、过采样率(OSR)为256时,峰值信噪谐波失真比(SNDR)和有效位数(ENOB)分别为75.29 dB和12.21 bit,芯片功耗仅为0.92 mW。芯片能在2.3~5.5 V宽电源电压范围内正常工作,可实现最大128 V/V的增益。适用于小型传感器的信号测量应用,可以满足小型传感器低功耗、高精度的需求。

基于FPGA的多片ADC同步设计与实现

本文通过利用模数转换器的测试模式可实现对多片ADC高速采集系统的同步设计。该设计方案,可保证相控阵雷达多通道的相位一致性,确保方位和俯仰角度测量的准确性。通过外部模拟信号源对该系统进行功能测试,并通过Matlab对测试结果进行分析,确定通道间的相位关系,对该设计方案的功能性及稳定性进行了验证。

Overview of Energy-Efficient Successive-Approximation Analog-to-Digital Converters: State-of-the-Art and a Design Example

This paper makes a review of state-of-the- arts designs of successive-approximation register analog-to-digital converters （SAR ADCs）. Methods and technique specifications are collected in view of innovative ideas. At the end of this paper, a design example is given to illustrate the procedure to design an SAR ADC. A new method, which extends the width of the internal clock, is also proposed to facilitate different sampling frequencies, which provides more time for the digital-to-analog convert （DAC） and comparator to settle. The 10 bit ADC is simulated in 0.13 μm CMOS process technology. The signal-to-noise and distortion ratio （SNDR） is 54.41 dB at a 10 MHz input with a 50 MS/s sampling rate, and the power is 330 μW.

SPLIT-ADC BASED DIGITAL BACKGROUND CALIBRATION FOR TIME-INTERLEAVED ADC

A novel Time-Interleaved Analog-to-Digital Converter (TIADC) digital background calibration for the mismatches of offsets, gain errors, and timing skews based on split-ADC is proposed. Firstly, the split-ADC channels in present TIADC architecture are designed to convert input signal at two different channel sampling rates so that redundant channel to facilitate pair permutation is avoided. Secondly, a high-order compensation scheme for correction of timing skew error is employed for effective calibration to preserve high-resolution when input frequency is high. Numerical simulation performed by MATLAB for a 14-bit TIADC based on 7 split-ADC channels shows that Signal-to-Noise and Distortion Ratio (SNDR) and Spurious Free Dynamic Range (SFDR) of the TIADC achieve 86.2 dBc and 106 dBc respectively after calibration with normalized input frequency near Nyquist frequency.

High Speed Electro-Absorption Modulators for Digital and Analog Optical Fiber Communications

An electro-absorption(EA)modulator is one of key components for optical fiber communications due to the high speed,small size,low voltage and integration ability with other semiconductor devices.A 40 Gb/s InGaAsP/InP multiplequantum-well(MQW)EA modulator monolithically integrated with a semiconductor optical amplifier(SOA)was fabricated for digital communications.The modulator capacitance was reduced to obtain 40 GHz bandwidth,and the SOA section helped reduce the insertion loss from 18 dB to 3 dB.InGaAlAs/InP MQW EA modulators have also been fabricated and characterized for analog optical fiber communications.A low driving voltage of 2.7 V and high spurious free dynamic range of 107 dB·Hz2/3 were estimated by static and dynamic measurements.

基于FPGA与AD/DA的JESD204B协议通信与控制模块设计

为了完成高速射频信号的采集与发射,设计了基于FPGA、模数转换器AD9680与数模转换器AD9144电路的通信与控制模块。硬件设计主要包含前端设计、时钟设计、控制部分设计。软件部分则详细阐述了程序结构、模块设计以及程序执行流程。为兼容各种不同的AD/DA芯片且便于移植复用,所有数据处理以及寄存器配置都在FPGA的处理系统(PS)部分完成,在可编程逻辑(PL)部分完成与PS以及外设的数据交互与存储。该软件整体可视作一个软件封装IP。使用FPGA为主控芯片与AD/DA完成10 Gbit/s的线速率JESD204B链路通信,并以2 GSa/s的转换速率进行数据采集与发射,验证了设计的正确性。

From Digital Analogs Through Recursive Machines to Quantum Computer

The report examines the evolution of computers from digital analogs through non-yon Neumann machines to quantum computers, which are also digital analogs. In the 60 years of digital analogs successfully developed at the Institute of Electromechanics of the USSR in Leningrad. An important stage in the development of non-classical multiprocessor machine performance and reliability has been the development of recursive machines, which was carried out at the Institute of Cybernetics led V.M.Glushkov and the Leningrad Institute of Aviation Instrumentation. The general approach to the synthesis is carried out through linguo- combinatorial modeling with structured uncertainty.

一种集成IIR滤波的三阶噪声整形逐次逼近ADC设计

针对经典噪声整形(Noise-Shaping,NS)无源逐次逼近型(Successive Approximation Register,SAR)模数转换器(Analog-to-Digital Converter,ADC)精度较低问题,提出了一种动态放大器与无限冲激响应(Infinite Impulse Response,IIR)滤波器级联的三阶NS-SAR ADC设计方法。利用动态放大器增益和IIR滤波器积分来补偿余量电压损失,以提高NS-SAR ADC的精度。同时,采用基于浮动反相器的放大器(Floating Inverter Amplifier,FIA)提高ADC的稳健性。基于0.18μm互补金属-氧化物-半导体(Complementary Metal Oxide Semiconductor,CMOS)工艺进行设计,实验结果表明,设计的ADC在考虑工艺-电压-温度波动的情况下,以10 bits电路结构实现了大于4.3 bits的有效位数提升;在1.8 V电源电压、2 kS/s采样速率和8倍过采样率条件下,信噪失真比为88.2 dB,功耗为1.05μW,能效优值为168.9 dB。与经典NS-SAR ADC设计相比,所提设计实现了较高的ADC精度。