With the continuous development of science and technology, digital signal processing is more and more widely used in various fields. Among them, the analog-to-digital converter (ADC) is one of the key components to co...With the continuous development of science and technology, digital signal processing is more and more widely used in various fields. Among them, the analog-to-digital converter (ADC) is one of the key components to convert analog signals to digital signals. As a common type of ADC, 12-bit sequential approximation analog-to-digital converter (SAR ADC) has attracted extensive attention for its performance and application. This paper aims to conduct in-depth research and analysis of 12-bit SAR ADC to meet the growing demands of digital signal processing. This article designs a 12-bit, successive approximation analog-to-digital converter (SAR ADC) with a sampling rate of 5 MS/s. The overall circuit adopts a fully differential structure, with key modules including DAC capacitor array, comparator, and control logic. According to the DAC circuit in this paper, a fully differential capacitor DAC array structure is proposed to reduce the area of layout DAC. The comparator uses a digital dynamic comparator to improve the ADC conversion speed. The chip is designed based on the SMIC180 nm CMOS process. The simulation results show that when the sampling rate is 5 MS/s, the effective bit of SAR ADC is 11.92 bit, the SNR is 74.62 dB, and the SFDR is 89.24 dB.展开更多
This paper makes a review of state-of-the- arts designs of successive-approximation register analog-to-digital converters (SAR ADCs). Methods and technique specifications are collected in view of innovative ideas. A...This paper makes a review of state-of-the- arts designs of successive-approximation register analog-to-digital converters (SAR ADCs). Methods and technique specifications are collected in view of innovative ideas. At the end of this paper, a design example is given to illustrate the procedure to design an SAR ADC. A new method, which extends the width of the internal clock, is also proposed to facilitate different sampling frequencies, which provides more time for the digital-to-analog convert (DAC) and comparator to settle. The 10 bit ADC is simulated in 0.13 μm CMOS process technology. The signal-to-noise and distortion ratio (SNDR) is 54.41 dB at a 10 MHz input with a 50 MS/s sampling rate, and the power is 330 μW.展开更多
Comparator offset cancellation and capacitor self-calibration techniques used in a successive approximation analog-to-digital converter (SA-ADC) are described. The calibration circuit works in parallel with the SAAD...Comparator offset cancellation and capacitor self-calibration techniques used in a successive approximation analog-to-digital converter (SA-ADC) are described. The calibration circuit works in parallel with the SAADC by adding additional calibration clock cycles to pursue high accuracy and low power consumption, and the calibrated resolution can be up to 14bit. This circuit is used in a 10bit 3Msps successive approximation ADC. This chip is realized with an SMIC 0. 18μm 1.8V process and occupies 0.25mm^2 . It consumes 3. 1mW when operating at 1.8MHz. The measured SINAD is 55. 9068dB, SFDR is 64. 5767dB, and THD is - 74. 8889dB when sampling a 320kHz sine wave.展开更多
The radiation effects on several properties (reference voltage, digital output logic voltage, and supply current) of dual 8-bit analog-to-digital (A/D) converters (AD9058) under various biased conditions are inv...The radiation effects on several properties (reference voltage, digital output logic voltage, and supply current) of dual 8-bit analog-to-digital (A/D) converters (AD9058) under various biased conditions are investigated in this paper. Gamma ray and 10-MeV proton irradiation are selected for a detailed evaluation and comparison. Based on the measurement results induced by the gamma ray with various dose rates, the devices exhibit enhanced low dose rate sensitivity (ELDRS) under zero and working bias conditions. Meanwhile, it is obvious that the ELDRS is more severe under the working bias condition than under the zero bias condition. The degradation of AD9058 does not display obvious ELDRS during 10-MeV proton irradiation with the selected flux.展开更多
A new technique which is named charge temporary storage technique (CTST) was presented to improve the linearity of a 1.5 bit/s pipelined analog-to-digital converter (ADC). The residual voltage was obtained from the sa...A new technique which is named charge temporary storage technique (CTST) was presented to improve the linearity of a 1.5 bit/s pipelined analog-to-digital converter (ADC). The residual voltage was obtained from the sampling capacitor, and the other capacitor was just a temporary storage of charge. Then, the linearity produced by the mismatch of these capacitors was eliminated without adding extra capacitor error-averaging amplifiers. The simulation results confirmed the high linearity and low dissipation of pipelined ADCs implemented in CTST, so CTST was a new method to implement high resolution, small size ADCs.展开更多
An all-optical analog-to-digital converter (ADC) based on the nonlinear effect in a silicon waveguide is a promising candidate for overcoming the limitation of electronic devices and is suitable for photonic integra...An all-optical analog-to-digital converter (ADC) based on the nonlinear effect in a silicon waveguide is a promising candidate for overcoming the limitation of electronic devices and is suitable for photonic integration. In this paper, a lumped time-delay compensation scheme with 2-bit quantization resolution is proposed. A strip silicon waveguide is designed and used to compensate for the entire time-delays of the optical pulses after a soliton self-frequency shift (SSFS) module within a wavelength range of 1550 nm-1580 nm. A dispersion coefficient as high as -19800 ps/(km.nm) with +0.5 ps/(km.nm) variation is predicted for the strip waveguide. The simulation results show that the maximum supportable sampling rate (MSSR) is 50.45 GSa/s with full width at half maximum (FWHM) variation less than 2.52 ps, along with the 2-bit effective- number-of-bit and Gray code output.展开更多
We propose a novel lumped time-delay compensation scheme for all-optical analog-to-digital conversion based on soliton self-frequency shift and optical interconnection techniques. A linearly chirped fiber Bragg gratin...We propose a novel lumped time-delay compensation scheme for all-optical analog-to-digital conversion based on soliton self-frequency shift and optical interconnection techniques. A linearly chirped fiber Bragg grating is optimally designed and used to compensate for the entire time-delays of the quantized pulses precisely. Simulation results show that the compensated coding pulses are well synchronized with a time difference less than 3.3 ps, which can support a maximum sampling rate of 151.52 GSa/s. The proposed scheme can efficiently reduce the structure complexity and cost of all-optical analog-to-digital conversion compared to the previous schemes with multiple optical time-delay lines.展开更多
A novel optical analog-to-digital converter based on optical time division multiplexing(OTDM) is described which uses electrooptic sampling and time-demultiplexing together with multiple electronic analog-to-digital c...A novel optical analog-to-digital converter based on optical time division multiplexing(OTDM) is described which uses electrooptic sampling and time-demultiplexing together with multiple electronic analog-to-digital converter(ADC). Compared with the previous scheme, the time-division multiplexer and the time-division demultiplexer are applied in the optical analog-to-digital converter(OADC) at the same time, the design of the OADC is simplified and the performance of the OADC based on time-division demultiplexer is improved. A core optical part of the system is demonstrated with a sample rate of 10 Gs/s. The signals in three channels are demultiplexed from the optical pulses.The result proves our scheme is feasible.展开更多
We considered the physiological mechanisms of functioning of the retina’s neural network. It is marked that the primary function of a neural network is an analog-to-digital conversion of the receptor potential of pho...We considered the physiological mechanisms of functioning of the retina’s neural network. It is marked that the primary function of a neural network is an analog-to-digital conversion of the receptor potential of photoreceptor into the pulse-to-digital signal to ganglion cells. We showed the role of different types of neurons in the work of analog-to-digital converter. We gave the equivalent circuit of this converter. We researched the mechanism of the numeric coding of the receptor potential of the photoreceptor.展开更多
A digital background calibration technique that corrects the capacitor mismatches error is proposed for successive approximation register analog-to-digital converter (SAR ADC). The technique is implemented in SAR ADC ...A digital background calibration technique that corrects the capacitor mismatches error is proposed for successive approximation register analog-to-digital converter (SAR ADC). The technique is implemented in SAR ADC which is based on tri-level switching. The termination capacitor in the Digital-to-Analog Converter (DAC) is regarded as a reference capacitor and the digital weights of all other unit capacitors are corrected with respect to the reference capacitor. To make a comparison between the size of the unit capacitor and that of the reference capacitor, each input sample is quantized twice. The unit capacitor being calibrated is swapped with the reference capacitor during the second conversion. The difference between the two conversion results is used to correct the digital weight of the unit capacitor under calibration. The calibration technique with two reference capacitors is presented to reduce the number of parameters to be estimated. Behavior simulation is performed to verify the proposed calibration technique by using a 12-bit SAR ADC with 3% random capacitor mismatch. The simulation results show that the Signal-to-Noise and Distortion Ratio (SNDR) is improved from 57.2 dB to 72.2 dB and the Spurious Free Dynamic Range (SFDR) is improved from 60.0 dB to 85.4 dB.展开更多
A 14-bit successive approximation analog-to-digital converter (SAR ADC) with capacitive calibration has been designed based on the SMIC. 18 μm CMOS process. The overall architecture is in fully differential form to e...A 14-bit successive approximation analog-to-digital converter (SAR ADC) with capacitive calibration has been designed based on the SMIC. 18 μm CMOS process. The overall architecture is in fully differential form to eliminate the effect caused by common mode noise. Meanwhile, the digital-to-analog converter (DAC) is a two-stage structure, which can greatly reduce the area of the capacitor array compared with the traditional DAC structure. The capacitance calibration module is mainly divided into the mismatch voltage acquisition phase and the calibration code backfill phase, which effectively reduces the impact of the DAC mismatch on the accuracy of the SAR ADC. The design of this paper is based on cadence platform simulation verification, simulation results show that when the sampling rate is 1 MS/s, the power supply voltage is 5 V and the reference voltage is 4.096 V, the effective number of bits (ENOB) of the ADC is 13.49 bit, and the signal-to-noise ratio (SNR) is 83.3 dB.展开更多
We investigate a channel-interleaved photonic analog-to-digital conversion(PADC)system’s ability to work stably over a long duration with an optimal driving voltage.The influence of optimum bias point drift of a Mach...We investigate a channel-interleaved photonic analog-to-digital conversion(PADC)system’s ability to work stably over a long duration with an optimal driving voltage.The influence of optimum bias point drift of a Mach–Zehnder modulator(MZM)-based photonic switch on this system was analyzed theoretically and experimentally.The feasibility of extracting feedback signals from the PADC system was derived.A high-stability channel-interleaved PADC was constructed by extracting a feedback signal from a parallel demultiplexing module to control the MZM-based photonic switch’s driving voltage.Consequently,the amplitude mismatch between the channels was limited to within 0.3 d B over 12 hours of operation.展开更多
A digital calibration technique for an ultra high-speed folding and interpolating analog-to-digital con- verter in 0.18-μm CMOS technology is presented. The similar digital calibration techniques are taken for high 3...A digital calibration technique for an ultra high-speed folding and interpolating analog-to-digital con- verter in 0.18-μm CMOS technology is presented. The similar digital calibration techniques are taken for high 3-bit flash converter and low 5-bit folding and interpolating converter, which are based on well-designed calibration reference, calibration DAC and comparators. The spice simulation and the measured results show the ADC produces 5.9 ENOB with calibration disabled and 7.2 ENOB with calibration enabled for high-frequency wide-bandwidth analog input.展开更多
This Letter theoretically and experimentally studies the response of photonic switching in a channel-interleaved photonic analog-to-digital converter(PADC) with high sampling rate and wide input frequency range. A fig...This Letter theoretically and experimentally studies the response of photonic switching in a channel-interleaved photonic analog-to-digital converter(PADC) with high sampling rate and wide input frequency range. A figure of merit(FoM) is introduced to evaluate the switching response of the PADC when a dual-output Mach–Zehnder modulator(MZM) serves as the photonic switch to parallelize the sampled pulse train into two channels. After the optimization of the FoM and utilization of the channel-mismatch compensation algorithm,the system bandwidth of PADC is expanded and the signal-to-distortion ratio is enhanced.展开更多
A feed-forward Common-Mode (CM) charge control circuit for a high-speed Charge-Domain (CO) pipelined Analog-to-Digital Converter (ADC) is presented herein. This study aims at solving the problem whereby the prec...A feed-forward Common-Mode (CM) charge control circuit for a high-speed Charge-Domain (CO) pipelined Analog-to-Digital Converter (ADC) is presented herein. This study aims at solving the problem whereby the precision of CD pipelined ADCs is restricted by the variation in input CM charge, which can compensate for CM charge errors caused by a variation in CM charge input in real time. Based on the feed-forward CM charge control circuit, a 12-bit 250-MS/s CD pipelined ADC is designed and realized using a 1P6M 0.18-μm CMOS process. The ADC achieved a Spurious Free Dynamic Range (SFDR) of 78.1 dB and a Signal-to-Noise-and-Distortion Ratio (SNDR) of 64.6 dB for a 20.1-MHz input; a SFDR of 74.9 dB and SNDR of 62.0 dB were achieved for a 239.9-MHz input at full sampling rate. The variation in signal-to-noise ratio was less than 3 dB over a 0-1.2 V input CM voltage range. The power consumption of the prototype ADC is only 85 mW at 1.8 V supply, and it occupies an active die area of 2.24 mm^2.展开更多
This Letter demonstrates the effectiveness of a high-speed high-resolution photonic analog-to-digital converter (PADC) for wideband signal detection. The PADC system is seeded by a high-speed actively mode locked la...This Letter demonstrates the effectiveness of a high-speed high-resolution photonic analog-to-digital converter (PADC) for wideband signal detection. The PADC system is seeded by a high-speed actively mode locked laser, and the sampling rate is multiplied via a time-wavelength interleaving scheme. According to the laboratory test, an X-band linear frequency modulation signal is detected and digitized by the PADC system. The channel mismatch effect in wideband signal detection is compensated via an algorithm based on a short-time Fourier transform. Consequently, the signal-to-distortion ratio (SDR) of the wideband signal detection is enhanced to the comparable SDR of the single-tone signal detection.展开更多
An all-optical analog-to-digital converter capable of sampling at 50GS/s is described. The ADC works in the frequency domain. The RF signal is sampled by electro-optically steerable gratings and quantized by a set of ...An all-optical analog-to-digital converter capable of sampling at 50GS/s is described. The ADC works in the frequency domain. The RF signal is sampled by electro-optically steerable gratings and quantized by a set of detectors with scalable apertures.展开更多
Apower-efficient 12-bit40-MS/spipelineanalog-to-digitalconverter(ADC)implementedina0.13 μm CMOS technology is presented. A novel CMOS bootstrapping switch, which offers a constant on-resistance over the entire inpu...Apower-efficient 12-bit40-MS/spipelineanalog-to-digitalconverter(ADC)implementedina0.13 μm CMOS technology is presented. A novel CMOS bootstrapping switch, which offers a constant on-resistance over the entire input signal range, is used at the sample-and-hold front-end to enhance the dynamic performance of the pipelined ADC. By implementing with 2.5-bit-per-stage and a simplified amplifier sharing architecture between two successive pipeline stages, a very competitive power consumption and small die area can be achieved. Meanwhile, the substrate-biasing-effect attenuated T-type switches are introduced to reduce the crosstalk between the two op- amp sharing successive stages. Moreover, a two-stage gain boosted recycling folded cascode (RFC) amplifier with hybrid frequency compensation is developed to further reduce the power consumption and maintain the ADC's performance simultaneously. The measured results imply that the ADC achieves a spurious-free dynamic range (SFDR) of 75.7 dB and a signal-to-noise-plus-distortion ratio (SNDR) of 62.74 dB with a 4.3 MHz input signal; the SNDR maintains over 58.25 dB for input signals up to 19.3MHz. The measured differential nonlinearity (DNL) and integral nonlinearity (INL) are -0.43 to +0.48 LSB and -1.62 to + 1.89 LSB respectively. The prototype ADC consumes 28.4 mW under a 1.2-V nominal power supply and 40 MHz sampling rate, transferring to a figure- of-merit (FOM) of 0.63 pJ per conversion-step.展开更多
A 2-Gsample/s 8-b analog-to-digital converter in 0.35μm BiCMOS process technology is presented. The ADC uses the unique folding and interpolating algorithm and dual-channel timing interleave multiplexing technology t...A 2-Gsample/s 8-b analog-to-digital converter in 0.35μm BiCMOS process technology is presented. The ADC uses the unique folding and interpolating algorithm and dual-channel timing interleave multiplexing technology to achieve a sampling rate of 2 GSPS.Digital calibration technology is used for the offset and gain corrections of the S/H circuit,the offset correction of preamplifier,and the gain and clock phase corrections between channels.As a result of testing,the ADC achieves 7.32 ENOB at an analog input of 484 MHz and 7.1 ENOB at Nyquist input after the chip is self-corrected.展开更多
A 20 Gsample/s photonic analog-to-digital converter is constructed using a 4-switching-wavelength repetitive sampling pulse source. The signal-to-noise and distortion ratio (SINAD) is measured to be 44.5 dB and corres...A 20 Gsample/s photonic analog-to-digital converter is constructed using a 4-switching-wavelength repetitive sampling pulse source. The signal-to-noise and distortion ratio (SINAD) is measured to be 44.5 dB and corresponds to 7 effective number of bits.展开更多
文摘With the continuous development of science and technology, digital signal processing is more and more widely used in various fields. Among them, the analog-to-digital converter (ADC) is one of the key components to convert analog signals to digital signals. As a common type of ADC, 12-bit sequential approximation analog-to-digital converter (SAR ADC) has attracted extensive attention for its performance and application. This paper aims to conduct in-depth research and analysis of 12-bit SAR ADC to meet the growing demands of digital signal processing. This article designs a 12-bit, successive approximation analog-to-digital converter (SAR ADC) with a sampling rate of 5 MS/s. The overall circuit adopts a fully differential structure, with key modules including DAC capacitor array, comparator, and control logic. According to the DAC circuit in this paper, a fully differential capacitor DAC array structure is proposed to reduce the area of layout DAC. The comparator uses a digital dynamic comparator to improve the ADC conversion speed. The chip is designed based on the SMIC180 nm CMOS process. The simulation results show that when the sampling rate is 5 MS/s, the effective bit of SAR ADC is 11.92 bit, the SNR is 74.62 dB, and the SFDR is 89.24 dB.
基金supported in part by the National Natural Science Foundation of China under Grant No.61006027the New Century Excellent Talents Program of the Ministry of Education of China under Grant No.NCET-10-0297the Fundamental Research Funds for Central Universities under Grant No.ZYGX2012J003
文摘This paper makes a review of state-of-the- arts designs of successive-approximation register analog-to-digital converters (SAR ADCs). Methods and technique specifications are collected in view of innovative ideas. At the end of this paper, a design example is given to illustrate the procedure to design an SAR ADC. A new method, which extends the width of the internal clock, is also proposed to facilitate different sampling frequencies, which provides more time for the digital-to-analog convert (DAC) and comparator to settle. The 10 bit ADC is simulated in 0.13 μm CMOS process technology. The signal-to-noise and distortion ratio (SNDR) is 54.41 dB at a 10 MHz input with a 50 MS/s sampling rate, and the power is 330 μW.
文摘Comparator offset cancellation and capacitor self-calibration techniques used in a successive approximation analog-to-digital converter (SA-ADC) are described. The calibration circuit works in parallel with the SAADC by adding additional calibration clock cycles to pursue high accuracy and low power consumption, and the calibrated resolution can be up to 14bit. This circuit is used in a 10bit 3Msps successive approximation ADC. This chip is realized with an SMIC 0. 18μm 1.8V process and occupies 0.25mm^2 . It consumes 3. 1mW when operating at 1.8MHz. The measured SINAD is 55. 9068dB, SFDR is 64. 5767dB, and THD is - 74. 8889dB when sampling a 320kHz sine wave.
基金supported by the National Natural Science Foundation of China (Grant No. 11205038)the China Postdoctoral Science Foundation (Grant No. 2012M510951)
文摘The radiation effects on several properties (reference voltage, digital output logic voltage, and supply current) of dual 8-bit analog-to-digital (A/D) converters (AD9058) under various biased conditions are investigated in this paper. Gamma ray and 10-MeV proton irradiation are selected for a detailed evaluation and comparison. Based on the measurement results induced by the gamma ray with various dose rates, the devices exhibit enhanced low dose rate sensitivity (ELDRS) under zero and working bias conditions. Meanwhile, it is obvious that the ELDRS is more severe under the working bias condition than under the zero bias condition. The degradation of AD9058 does not display obvious ELDRS during 10-MeV proton irradiation with the selected flux.
基金The National Science Fund for Creative Re-search Groups( Grant No 60521002 )Shanghai Natural Science Foundation (GrantNo 037062022)
文摘A new technique which is named charge temporary storage technique (CTST) was presented to improve the linearity of a 1.5 bit/s pipelined analog-to-digital converter (ADC). The residual voltage was obtained from the sampling capacitor, and the other capacitor was just a temporary storage of charge. Then, the linearity produced by the mismatch of these capacitors was eliminated without adding extra capacitor error-averaging amplifiers. The simulation results confirmed the high linearity and low dissipation of pipelined ADCs implemented in CTST, so CTST was a new method to implement high resolution, small size ADCs.
基金supported by the Fundamental Research Funds for the Central Universities,China(Grant No.FRF-TP-15-030A1)China Postdoctoral Science Foundation(Grant No.2015M580978)
文摘An all-optical analog-to-digital converter (ADC) based on the nonlinear effect in a silicon waveguide is a promising candidate for overcoming the limitation of electronic devices and is suitable for photonic integration. In this paper, a lumped time-delay compensation scheme with 2-bit quantization resolution is proposed. A strip silicon waveguide is designed and used to compensate for the entire time-delays of the optical pulses after a soliton self-frequency shift (SSFS) module within a wavelength range of 1550 nm-1580 nm. A dispersion coefficient as high as -19800 ps/(km.nm) with +0.5 ps/(km.nm) variation is predicted for the strip waveguide. The simulation results show that the maximum supportable sampling rate (MSSR) is 50.45 GSa/s with full width at half maximum (FWHM) variation less than 2.52 ps, along with the 2-bit effective- number-of-bit and Gray code output.
基金Project supported by the National Basic Research Program,China(Grant Nos.2010CB327605 and 2010CB328300)the National High-Technology Research and Development Program of China(Grant No.2013AA031501)+7 种基金the National Natural Science Foundation of China(Grant No.61307109)the Specialized Research Fund for the Doctoral Program of Higher Education of China(Grant No.20120005120021)the Fundamental Research Funds for the Central Universities,China(Grant No.2013RC1202)the Program for New Century Excellent Talents in University,China(Grant No.NECT-11-0596)the Beijing Nova Program,China(Grant No.2011066)the Fund of State Key Laboratory of Information Photonics and Optical Communications(Beijing University of Posts and Telecommunications) Chinathe China Postdoctoral Science Foundation(Grant No.2012M511826)the Postdoctoral Science Foundation of Guangdong Province,China(Grant No.244331)
文摘We propose a novel lumped time-delay compensation scheme for all-optical analog-to-digital conversion based on soliton self-frequency shift and optical interconnection techniques. A linearly chirped fiber Bragg grating is optimally designed and used to compensate for the entire time-delays of the quantized pulses precisely. Simulation results show that the compensated coding pulses are well synchronized with a time difference less than 3.3 ps, which can support a maximum sampling rate of 151.52 GSa/s. The proposed scheme can efficiently reduce the structure complexity and cost of all-optical analog-to-digital conversion compared to the previous schemes with multiple optical time-delay lines.
文摘A novel optical analog-to-digital converter based on optical time division multiplexing(OTDM) is described which uses electrooptic sampling and time-demultiplexing together with multiple electronic analog-to-digital converter(ADC). Compared with the previous scheme, the time-division multiplexer and the time-division demultiplexer are applied in the optical analog-to-digital converter(OADC) at the same time, the design of the OADC is simplified and the performance of the OADC based on time-division demultiplexer is improved. A core optical part of the system is demonstrated with a sample rate of 10 Gs/s. The signals in three channels are demultiplexed from the optical pulses.The result proves our scheme is feasible.
文摘We considered the physiological mechanisms of functioning of the retina’s neural network. It is marked that the primary function of a neural network is an analog-to-digital conversion of the receptor potential of photoreceptor into the pulse-to-digital signal to ganglion cells. We showed the role of different types of neurons in the work of analog-to-digital converter. We gave the equivalent circuit of this converter. We researched the mechanism of the numeric coding of the receptor potential of the photoreceptor.
文摘A digital background calibration technique that corrects the capacitor mismatches error is proposed for successive approximation register analog-to-digital converter (SAR ADC). The technique is implemented in SAR ADC which is based on tri-level switching. The termination capacitor in the Digital-to-Analog Converter (DAC) is regarded as a reference capacitor and the digital weights of all other unit capacitors are corrected with respect to the reference capacitor. To make a comparison between the size of the unit capacitor and that of the reference capacitor, each input sample is quantized twice. The unit capacitor being calibrated is swapped with the reference capacitor during the second conversion. The difference between the two conversion results is used to correct the digital weight of the unit capacitor under calibration. The calibration technique with two reference capacitors is presented to reduce the number of parameters to be estimated. Behavior simulation is performed to verify the proposed calibration technique by using a 12-bit SAR ADC with 3% random capacitor mismatch. The simulation results show that the Signal-to-Noise and Distortion Ratio (SNDR) is improved from 57.2 dB to 72.2 dB and the Spurious Free Dynamic Range (SFDR) is improved from 60.0 dB to 85.4 dB.
文摘A 14-bit successive approximation analog-to-digital converter (SAR ADC) with capacitive calibration has been designed based on the SMIC. 18 μm CMOS process. The overall architecture is in fully differential form to eliminate the effect caused by common mode noise. Meanwhile, the digital-to-analog converter (DAC) is a two-stage structure, which can greatly reduce the area of the capacitor array compared with the traditional DAC structure. The capacitance calibration module is mainly divided into the mismatch voltage acquisition phase and the calibration code backfill phase, which effectively reduces the impact of the DAC mismatch on the accuracy of the SAR ADC. The design of this paper is based on cadence platform simulation verification, simulation results show that when the sampling rate is 1 MS/s, the power supply voltage is 5 V and the reference voltage is 4.096 V, the effective number of bits (ENOB) of the ADC is 13.49 bit, and the signal-to-noise ratio (SNR) is 83.3 dB.
基金This work was partially supported by the National Natural Science Foundation of China(Nos.61571292,61535006,and 61822508).
文摘We investigate a channel-interleaved photonic analog-to-digital conversion(PADC)system’s ability to work stably over a long duration with an optimal driving voltage.The influence of optimum bias point drift of a Mach–Zehnder modulator(MZM)-based photonic switch on this system was analyzed theoretically and experimentally.The feasibility of extracting feedback signals from the PADC system was derived.A high-stability channel-interleaved PADC was constructed by extracting a feedback signal from a parallel demultiplexing module to control the MZM-based photonic switch’s driving voltage.Consequently,the amplitude mismatch between the channels was limited to within 0.3 d B over 12 hours of operation.
基金Project supported by the National Natural Science Foundation of China(Nos.60906009,60773025)the Postdoctoral Science Foundation of China(No.20090451423)the National Labs of Analog Integrated Circuits Foundation(No.9140C0901110902)
文摘A digital calibration technique for an ultra high-speed folding and interpolating analog-to-digital con- verter in 0.18-μm CMOS technology is presented. The similar digital calibration techniques are taken for high 3-bit flash converter and low 5-bit folding and interpolating converter, which are based on well-designed calibration reference, calibration DAC and comparators. The spice simulation and the measured results show the ADC produces 5.9 ENOB with calibration disabled and 7.2 ENOB with calibration enabled for high-frequency wide-bandwidth analog input.
基金partially supported by the National Natural Science Foundation of China(Nos.61822508,61571292,and 61535006)
文摘This Letter theoretically and experimentally studies the response of photonic switching in a channel-interleaved photonic analog-to-digital converter(PADC) with high sampling rate and wide input frequency range. A figure of merit(FoM) is introduced to evaluate the switching response of the PADC when a dual-output Mach–Zehnder modulator(MZM) serves as the photonic switch to parallelize the sampled pulse train into two channels. After the optimization of the FoM and utilization of the channel-mismatch compensation algorithm,the system bandwidth of PADC is expanded and the signal-to-distortion ratio is enhanced.
基金supported by National Natural Science Foundation of China under grant No.61704161Key Project of Natural Science of Anhui Provincial Department of Education under grant No.KJ2017A396
文摘A feed-forward Common-Mode (CM) charge control circuit for a high-speed Charge-Domain (CO) pipelined Analog-to-Digital Converter (ADC) is presented herein. This study aims at solving the problem whereby the precision of CD pipelined ADCs is restricted by the variation in input CM charge, which can compensate for CM charge errors caused by a variation in CM charge input in real time. Based on the feed-forward CM charge control circuit, a 12-bit 250-MS/s CD pipelined ADC is designed and realized using a 1P6M 0.18-μm CMOS process. The ADC achieved a Spurious Free Dynamic Range (SFDR) of 78.1 dB and a Signal-to-Noise-and-Distortion Ratio (SNDR) of 64.6 dB for a 20.1-MHz input; a SFDR of 74.9 dB and SNDR of 62.0 dB were achieved for a 239.9-MHz input at full sampling rate. The variation in signal-to-noise ratio was less than 3 dB over a 0-1.2 V input CM voltage range. The power consumption of the prototype ADC is only 85 mW at 1.8 V supply, and it occupies an active die area of 2.24 mm^2.
基金partially supported by the National Natural Science Foundation of China(Nos.61571292and 61535006)
文摘This Letter demonstrates the effectiveness of a high-speed high-resolution photonic analog-to-digital converter (PADC) for wideband signal detection. The PADC system is seeded by a high-speed actively mode locked laser, and the sampling rate is multiplied via a time-wavelength interleaving scheme. According to the laboratory test, an X-band linear frequency modulation signal is detected and digitized by the PADC system. The channel mismatch effect in wideband signal detection is compensated via an algorithm based on a short-time Fourier transform. Consequently, the signal-to-distortion ratio (SDR) of the wideband signal detection is enhanced to the comparable SDR of the single-tone signal detection.
文摘An all-optical analog-to-digital converter capable of sampling at 50GS/s is described. The ADC works in the frequency domain. The RF signal is sampled by electro-optically steerable gratings and quantized by a set of detectors with scalable apertures.
基金Project supported by the National Science and Technology Major Projects of China(No.2012ZX03001018-001)the Fundamental Research Funds for the Central Universities,China(No.K50511250006)
文摘Apower-efficient 12-bit40-MS/spipelineanalog-to-digitalconverter(ADC)implementedina0.13 μm CMOS technology is presented. A novel CMOS bootstrapping switch, which offers a constant on-resistance over the entire input signal range, is used at the sample-and-hold front-end to enhance the dynamic performance of the pipelined ADC. By implementing with 2.5-bit-per-stage and a simplified amplifier sharing architecture between two successive pipeline stages, a very competitive power consumption and small die area can be achieved. Meanwhile, the substrate-biasing-effect attenuated T-type switches are introduced to reduce the crosstalk between the two op- amp sharing successive stages. Moreover, a two-stage gain boosted recycling folded cascode (RFC) amplifier with hybrid frequency compensation is developed to further reduce the power consumption and maintain the ADC's performance simultaneously. The measured results imply that the ADC achieves a spurious-free dynamic range (SFDR) of 75.7 dB and a signal-to-noise-plus-distortion ratio (SNDR) of 62.74 dB with a 4.3 MHz input signal; the SNDR maintains over 58.25 dB for input signals up to 19.3MHz. The measured differential nonlinearity (DNL) and integral nonlinearity (INL) are -0.43 to +0.48 LSB and -1.62 to + 1.89 LSB respectively. The prototype ADC consumes 28.4 mW under a 1.2-V nominal power supply and 40 MHz sampling rate, transferring to a figure- of-merit (FOM) of 0.63 pJ per conversion-step.
文摘A 2-Gsample/s 8-b analog-to-digital converter in 0.35μm BiCMOS process technology is presented. The ADC uses the unique folding and interpolating algorithm and dual-channel timing interleave multiplexing technology to achieve a sampling rate of 2 GSPS.Digital calibration technology is used for the offset and gain corrections of the S/H circuit,the offset correction of preamplifier,and the gain and clock phase corrections between channels.As a result of testing,the ADC achieves 7.32 ENOB at an analog input of 484 MHz and 7.1 ENOB at Nyquist input after the chip is self-corrected.
文摘A 20 Gsample/s photonic analog-to-digital converter is constructed using a 4-switching-wavelength repetitive sampling pulse source. The signal-to-noise and distortion ratio (SINAD) is measured to be 44.5 dB and corresponds to 7 effective number of bits.