Area optimization of parallel Chien search architecture for Reed-Solomon(255,239) decoder

A global optimization algorithm （GOA） for parallel Chien search circuit in Reed-Solomon （RS） （255,239） decoder is presented. By finding out the common modulo 2 additions within groups of Galois field （GF） multipliers and pre-computing the common items, the GOA can reduce the number of XOR gates efficiently and thus reduce the circuit area. Different from other local optimization algorithms, the GOA is a global one. When there are more than one maximum matches at a time, the best match choice in the GOA has the least impact on the final result by only choosing the pair with the smallest relational value instead of choosing a pair randomly. The results show that the area of parallel Chien search circuits can be reduced by 51% compared to the direct implementation when the group-based GOA is used for GF multipliers and by 26% if applying the GOA to GF multipliers separately. This optimization scheme can be widely used in general parallel architecture in which many GF multipliers are involved.

A Low Power/Area Digital FIR Filter Design Based on PRF Framework

A novel DSP to ASIC (Application Specific Integrated Circuit) architecture design methodology is presented in this paper for reducing power/area consumption. Traditional methods always focus on optimizing hardware structure or algorithm separately. The authors propose a new method called PRF (Paralleling Reducing Folding) framework to combine hardware optimization with algorithm simplification. In the first step, paralleling, unfolding technology is applied to divide one data path into several channels and expose the redundancy of the algorithm. In the second step, reducing, decoupling theory is used to reduce computational complexity. In the last step, folding, time multiplexing method is used to merge similar components. As an exoteric methodology framework, many optimization methods can be integrated into the PRF framework. To optimize a 3N taps FIR (Fincte Impact Response) and obtain a content result, PRF methodology framework is applied.

Open critical area model and extraction algorithm based on the net flow-axis

In the integrated circuit manufacturing process, the critical area extraction is a bottleneck to the layout optimization and the integrated circuit yield estimation. In this paper, we study the problem that the missing material defects may result in the open circuit fault. Combining the mathematical morphology theory, we present a new computation model and a novel extraction algorithm for the open critical area based on the net flow-axis. Firstly, we find the net flow-axis for different nets. Then, the net flow-edges based on the net flow-axis are obtained. Finally, we can extract the open critical area by the mathematical morphology. Compared with the existing methods, the nets need not to divide into the horizontal nets and the vertical nets, and the experimental results show that our model and algorithm can accurately extract the size of the open critical area and obtain the location information of the open circuit critical area.

FPGA Implementation of Elliptic-Curve Diffie Hellman Protocol

This paper presents an efficient crypto processor architecture for key agreement using ECDH(Elliptic-curve Diffie Hellman)protocol over GF2163.The composition of our key-agreement architecture is expressed in consisting of the following:(i)Elliptic-curve Point Multiplication architecture for public key generation(DESIGN-I)and(ii)integration of DESIGN-I with two additional routing multiplexers and a controller for shared key generation(DESIGN-II).The arithmetic operators used in DESIGN-I and DESIGNII contain an adder,squarer,a multiplier and inversion.A simple shift and add multiplication method is employed to retain lower hardware resources.Moreover,an essential inversion operation is operated using the Itoh-Tsujii algorithm with similar hardware resources of used squarer and multiplier units.The proposed architecture is implemented in a Verilog HDL.The implementation results are given on a Xilinx Virtex-7 FPGA(field-programmable gate array)device.For DESIGN-I and DESIGN-II over GF2163,(i)the utilized Slices are 3983 and 4037,(ii)the time to compute one public key and a shared secret is 553.7μs and 1170.7μs and(iii)the consumed power is 29μW and 57μW.Consequently,the achieved area optimized and power reduced results show that the proposed ECDH architecture is a suitable alternative(to generate a shared secret)for the applications that require low hardware resources and power consumption.

Multi-objective intelligent coordinating optimization blending system based on qualitative and quantitative synthetic model

A multi-objective intelligent coordinating optimization strategy based on qualitative and quantitative synthetic model for Pb-Zn sintering blending process was proposed to obtain optimal mixture ratio. The mechanism and neural network quantitative models for predicting compositions and rule models for expert reasoning were constructed based on statistical data and empirical knowledge. An expert reasoning method based on these models were proposed to solve blending optimization problem, including multi-objective optimization for the first blending process and area optimization for the second blending process, and to determine optimal mixture ratio which will meet the requirement of intelligent coordination. The results show that the qualified rates of agglomerate Pb, Zn and S compositions are increased by 7.1%, 6.5% and 6.9%, respectively, and the fluctuation of sintering permeability is reduced by 7.0%, which effectively stabilizes the agglomerate compositions and the permeability.

Discrete ternary particle swarm optimization for area optimization of MPRM circuits

Having the advantage of simplicity, robustness and low computational costs, the particle swarm optimization （PSO） algorithm is a powerful evolutionary computation tool for synthesis and optimization of Reed- Muller logic based circuits. Exploring discrete PSO and probabilistic transition rules, the discrete ternary particle swarm optimization （DTPSO） is proposed for mixed polarity Reed-Muller （MPRM） circuits. According to the characteristics of mixed polarity OR/XNOR expression, a tabular technique is improved, and it is applied in the polarity conversion of MPRM functions. DTPSO is introduced to search the best polarity for an area of MPRM circuits by building parameter mapping relationships between particles and polarities. The computational results show that the proposed DTPSO outperforms the reported method using maxterm conversion starting from POS Boolean functions. The average saving in the number of terms is about 11.5%; the algorithm is quite efficient in terms of CPU time and achieves 12.2% improvement on average.

A Power and Area Optimization Approach of Mixed Polarity Reed-Muller Expression for Incompletely Specified Boolean Functions

The power and area optimization of Reed-Muller （RM） circuits has been widely concerned. However, almost none of the exiting power and area optimization approaches can obtain all the Pareto optimal solutions of the original problem and are efficient enough. Moreover, they have not considered the don＇t care terms, which makes the circuit performance unable to be further optimized. In this paper, we propose a power and area optimization approach of mixed polarity RM expression （MPRM） for incompletely specified Boolean functions based on Non-Dominated Sorting Genetic Algorithm II （NSGA-II）. Firstly, the incompletely specified Boolean function is transformed into zero polarity incompletely specified MPRM （ISMPRM） by using a novel ISMPRM acquisition algorithm. Secondly, the polarity and allocation of don＇t care terms of ISMPRM is encoded as chromosome. Lastly, the Pareto optimal solutions are obtained by using NSGA-II, in which MPRM corresponding to the given chromosome is obtained by using a chromosome conversion algorithm. The results on incompletely specified Boolean functions and MCNC benchmark circuits show that a significant power and area improvement can be made compared with the existing power and area optimization approaches of RM circuits.

PMGA and its application in area and power optimization for ternary FPRM circuit

Based on the research of population migration algorithms （PMAs）, a population migration genetic algo- rithm （PMGA） is proposed, combining a PMA with a genetic algorithm. A scheme of area and power optimization for a ternary FPRM circuit is proposed by using the PMGA. Firstly, according to the ternary FPRM logic function expression, area and power estimation models are established. Secondly, the PMGA is used to search for the best area and power polarity. Finally, 10 MCNC Benchmark circuits are used to verify the effectiveness of the proposed method. The results show that the ternary FPRM circuits optimized by the PMGA saved 13.33% area and 20.00% power on average than the corresponding FPRM circuits optimized by a whole annealing genetic algorithm.

Identifying the sensitive area in adaptive observation for predicting the upstream Kuroshio transport variation in a 3-D ocean model

Using the conditional nonlinear optimal perturbation(CNOP) approach, sensitive areas of adaptive observation for predicting the seasonal reduction of the upstream Kuroshio transport(UKT) were investigated in the Regional Ocean Modeling System(ROMS). The vertically integrated energy scheme was utilized to identify sensitive areas based on two factors: the specific energy scheme and sensitive area size. Totally 27 sensitive areas, characterized by three energy schemes and nine sensitive area sizes, were evaluated. The results show that the total energy(TE) scheme was the most effective because it includes both the kinetic and potential components of CNOP. Generally, larger sensitive areas led to better predictions. The size of 0.5% of the model domain was chosen after balancing the effectiveness and efficiency of adaptive observation. The optimal sensitive area OSen was determined accordingly. Sensitivity experiments on OSen were then conducted, and the following results were obtained:(1) In OSen, initial errors with CNOP or CNOP-like patterns were more likely to yield worse predictions, and the CNOP pattern was the most unstable.(2) Initial errors in OSen rather than in other regions tended to cause larger prediction errors. Therefore, adaptive observation in OSen can be more beneficial for predicting the seasonal reduction of UKT.

Entransy dissipation analysis and optimization of separated heat pipe system

Seperated heat pipe systems are widely used in the fields of waste heat recovery and air conditioning due to their high heat transfer capability,and optimization of heat transfer process plays an important role in high-efficiency energy utilization and energy conservation.In this paper,the entransy dissipation analysis is conducted for the separated heat pipe system,and the result indicates that minimum thermal resistance principle is applicable to the optimization of the separated heat pipe system.Whether in the applications of waste heat recovery or air conditioning,the smaller the entransy-dissipation-based thermal re-sistance of the separated heat pipe system is,the better the heat transfer performance will be.Based on the minimum thermal resistance principle,the optimal area allocation relationship between evaporator and condenser is deduced,which is numeri-cally verified in the optimation design of separated heat pipe system.

An IP-oriented 11-bit 160 MS/s 2-channel current-steering DAC

This paper presents an 11-bit 160 MS/s 2-channel current-steering digital-to-analog converter（DAC）IP. The circuit and layout are carefully designed to optimize its performance and area. A 6-2-3 segmented structure is used for the trade-off among linearity, area and layout complexity. The sizes of current source transistors are calculated out according to the process matching parameter. The unary current cells are placed in a one-dimension distribution to simplify the layout routing, spare area and wiring layer. Their sequences are also carefully designed to reduce integral nonlinearity. The test result presents an SFDR of 72 dBc at 4.88 MHz input signal with DNL ≤60.25 LSB, INL ≤6 0.8 LSB. The full-scale output current is 5 m A with a 2.5 V analog power supply. The core of each channel occupies 0.08 mm^2 in a 1P-8M 55 nm CMOS process.