Open critical area model and extraction algorithm based on the net flow-axis

In the integrated circuit manufacturing process, the critical area extraction is a bottleneck to the layout optimization and the integrated circuit yield estimation. In this paper, we study the problem that the missing material defects may result in the open circuit fault. Combining the mathematical morphology theory, we present a new computation model and a novel extraction algorithm for the open critical area based on the net flow-axis. Firstly, we find the net flow-axis for different nets. Then, the net flow-edges based on the net flow-axis are obtained. Finally, we can extract the open critical area by the mathematical morphology. Compared with the existing methods, the nets need not to divide into the horizontal nets and the vertical nets, and the experimental results show that our model and algorithm can accurately extract the size of the open critical area and obtain the location information of the open circuit critical area.

OPTIMAL HARVESTING AND STABILITY FOR FISHING MODELS WITH STAGE STRUCTURE IN INSHORE-OFFSHORE AREAS

A fishing model with stage structure in inshore and offshore areas is considered.Steady states of the dynamical system representing fishery are derived and their local,as well as global,stability is discussed.The optimal harvest policy is formulated and solved as an optimal control problem.A numerical example is given to illustrate the solution procedure.

FPGA Implementation of Elliptic-Curve Diffie Hellman Protocol

This paper presents an efficient crypto processor architecture for key agreement using ECDH(Elliptic-curve Diffie Hellman)protocol over GF2163.The composition of our key-agreement architecture is expressed in consisting of the following:(i)Elliptic-curve Point Multiplication architecture for public key generation(DESIGN-I)and(ii)integration of DESIGN-I with two additional routing multiplexers and a controller for shared key generation(DESIGN-II).The arithmetic operators used in DESIGN-I and DESIGNII contain an adder,squarer,a multiplier and inversion.A simple shift and add multiplication method is employed to retain lower hardware resources.Moreover,an essential inversion operation is operated using the Itoh-Tsujii algorithm with similar hardware resources of used squarer and multiplier units.The proposed architecture is implemented in a Verilog HDL.The implementation results are given on a Xilinx Virtex-7 FPGA(field-programmable gate array)device.For DESIGN-I and DESIGN-II over GF2163,(i)the utilized Slices are 3983 and 4037,(ii)the time to compute one public key and a shared secret is 553.7μs and 1170.7μs and(iii)the consumed power is 29μW and 57μW.Consequently,the achieved area optimized and power reduced results show that the proposed ECDH architecture is a suitable alternative(to generate a shared secret)for the applications that require low hardware resources and power consumption.

Discrete ternary particle swarm optimization for area optimization of MPRM circuits

Having the advantage of simplicity, robustness and low computational costs, the particle swarm optimization （PSO） algorithm is a powerful evolutionary computation tool for synthesis and optimization of Reed- Muller logic based circuits. Exploring discrete PSO and probabilistic transition rules, the discrete ternary particle swarm optimization （DTPSO） is proposed for mixed polarity Reed-Muller （MPRM） circuits. According to the characteristics of mixed polarity OR/XNOR expression, a tabular technique is improved, and it is applied in the polarity conversion of MPRM functions. DTPSO is introduced to search the best polarity for an area of MPRM circuits by building parameter mapping relationships between particles and polarities. The computational results show that the proposed DTPSO outperforms the reported method using maxterm conversion starting from POS Boolean functions. The average saving in the number of terms is about 11.5%; the algorithm is quite efficient in terms of CPU time and achieves 12.2% improvement on average.

A Power and Area Optimization Approach of Mixed Polarity Reed-Muller Expression for Incompletely Specified Boolean Functions

The power and area optimization of Reed-Muller （RM） circuits has been widely concerned. However, almost none of the exiting power and area optimization approaches can obtain all the Pareto optimal solutions of the original problem and are efficient enough. Moreover, they have not considered the don＇t care terms, which makes the circuit performance unable to be further optimized. In this paper, we propose a power and area optimization approach of mixed polarity RM expression （MPRM） for incompletely specified Boolean functions based on Non-Dominated Sorting Genetic Algorithm II （NSGA-II）. Firstly, the incompletely specified Boolean function is transformed into zero polarity incompletely specified MPRM （ISMPRM） by using a novel ISMPRM acquisition algorithm. Secondly, the polarity and allocation of don＇t care terms of ISMPRM is encoded as chromosome. Lastly, the Pareto optimal solutions are obtained by using NSGA-II, in which MPRM corresponding to the given chromosome is obtained by using a chromosome conversion algorithm. The results on incompletely specified Boolean functions and MCNC benchmark circuits show that a significant power and area improvement can be made compared with the existing power and area optimization approaches of RM circuits.

PMGA and its application in area and power optimization for ternary FPRM circuit

Based on the research of population migration algorithms （PMAs）, a population migration genetic algo- rithm （PMGA） is proposed, combining a PMA with a genetic algorithm. A scheme of area and power optimization for a ternary FPRM circuit is proposed by using the PMGA. Firstly, according to the ternary FPRM logic function expression, area and power estimation models are established. Secondly, the PMGA is used to search for the best area and power polarity. Finally, 10 MCNC Benchmark circuits are used to verify the effectiveness of the proposed method. The results show that the ternary FPRM circuits optimized by the PMGA saved 13.33% area and 20.00% power on average than the corresponding FPRM circuits optimized by a whole annealing genetic algorithm.

An IP-oriented 11-bit 160 MS/s 2-channel current-steering DAC

This paper presents an 11-bit 160 MS/s 2-channel current-steering digital-to-analog converter（DAC）IP. The circuit and layout are carefully designed to optimize its performance and area. A 6-2-3 segmented structure is used for the trade-off among linearity, area and layout complexity. The sizes of current source transistors are calculated out according to the process matching parameter. The unary current cells are placed in a one-dimension distribution to simplify the layout routing, spare area and wiring layer. Their sequences are also carefully designed to reduce integral nonlinearity. The test result presents an SFDR of 72 dBc at 4.88 MHz input signal with DNL ≤60.25 LSB, INL ≤6 0.8 LSB. The full-scale output current is 5 m A with a 2.5 V analog power supply. The core of each channel occupies 0.08 mm^2 in a 1P-8M 55 nm CMOS process.