A high voltage BCD process using thin epitaxial technology is developed for high voltage applications. Compared to conventional thick expitaxial technology, the thickness of the n-type epitaxial layer is reduced to 9...A high voltage BCD process using thin epitaxial technology is developed for high voltage applications. Compared to conventional thick expitaxial technology, the thickness of the n-type epitaxial layer is reduced to 9μm,and the diffusion processing time needed for forming junction isolation diffusions is substantially reduced. The isolation diffusions have a smaller lateral extent and occupy less chip area. High voltage double RESURF LD- MOS with a breakdown voltage of up to 900V,as well as low voltage CMOS and BJT,are achieved using this high voltage BCD compatible process. An experimental high voltage half bridge gate drive IC using a coupled level shift structure is also successfully implemented, and the high side floating offset voltage in the half bridge drive IC is 880V. The major features of this process for high voltage applications are also clearly demonstrated.展开更多
提出一种蓄电池充电控制芯片的设计,具有恒流、恒压、过压、浮充等多种不同充电模式,可以在外部微处理器的支持下针对不同种类电池和应用场合的需要实现电池的高效优化充电。讨论并给出了芯片的系统组成及主要电路的设计,在1.5μm 50 V ...提出一种蓄电池充电控制芯片的设计,具有恒流、恒压、过压、浮充等多种不同充电模式,可以在外部微处理器的支持下针对不同种类电池和应用场合的需要实现电池的高效优化充电。讨论并给出了芯片的系统组成及主要电路的设计,在1.5μm 50 V BCD(Bipolar-CMOS-DMOS)工艺下予以实现。测试结果表明芯片工作正常,电路功能及芯片预期的主要功能已成功实现。展开更多
A 700 V BCD technology platform is presented for high voltage applications. An important feature is that all the devices have been realized by using a fully implanted technology in a p-type single crystal without an e...A 700 V BCD technology platform is presented for high voltage applications. An important feature is that all the devices have been realized by using a fully implanted technology in a p-type single crystal without an epitaxial or a buried layer. An economical manufacturing process, requiring only 10 masking steps, yields a broad range of MOS and bipolar components integrated on a common substrate, including 700 V nLDMOS, 200 V nLDMOS, 80 V nLDMOS, 60 V nLDMOS, 40 V nLDMOS, 700 V nJFET, and low voltage devices. A robust double RESURF nLDMOS with a breakdown voltage of 800 V and specific on-resistance of 206.2 mf2.cm2 is successfully optimized and realized. The results of this technology are low fabrication cost, simple process and small chip area for PIC products.展开更多
A new semi-insulation structure in which one isolated island is connected to the substrate was pro- posed. Based on this semi-insulation structure, an advanced BCD technology which can integrate a vertical de- vice wi...A new semi-insulation structure in which one isolated island is connected to the substrate was pro- posed. Based on this semi-insulation structure, an advanced BCD technology which can integrate a vertical de- vice without extra internal interconnection structure was presented. The manufacturing of the new semi-insulation structure employed multi-epitaxy and selectively multi-doping. Isolated islands are insulated with the substrate by reverse-biased PN junctions. Adjacent isolated islands are insulated by isolation wall or deep dielectric trenches. The proposed semi-insulation structure and devices fixed in it were simulated through two-dimensional numerical computer simulators. Based on the new BCD technology, a smart power integrated circuit was designed and fabri- cated. The simulated and tested results of Vertical DMOS, MOSFETs, BJTs, resistors and diodes indicated that the proposed semi-insulation structure is reasonable and the advanced BCD technology is validated.展开更多
为了提高压电传感器测量系统的集成度,采用1μm高压双极—互补金属氧化物半导体—双重扩散金属氧化物半导体(BCD)工艺,设计了一种适用于压电传感器的信号调理及输出芯片。集成了电压放大型阻抗变换电路、可调增益放大电路、二线制电流...为了提高压电传感器测量系统的集成度,采用1μm高压双极—互补金属氧化物半导体—双重扩散金属氧化物半导体(BCD)工艺,设计了一种适用于压电传感器的信号调理及输出芯片。集成了电压放大型阻抗变换电路、可调增益放大电路、二线制电流输出电路。仿真结果表明:芯片具有输入阻抗高,单位增益带宽大,总增益可调范围广等特点,在12~24 V宽供电范围下可正常工作,耗电仅为3.1 m A。展开更多
文摘A high voltage BCD process using thin epitaxial technology is developed for high voltage applications. Compared to conventional thick expitaxial technology, the thickness of the n-type epitaxial layer is reduced to 9μm,and the diffusion processing time needed for forming junction isolation diffusions is substantially reduced. The isolation diffusions have a smaller lateral extent and occupy less chip area. High voltage double RESURF LD- MOS with a breakdown voltage of up to 900V,as well as low voltage CMOS and BJT,are achieved using this high voltage BCD compatible process. An experimental high voltage half bridge gate drive IC using a coupled level shift structure is also successfully implemented, and the high side floating offset voltage in the half bridge drive IC is 880V. The major features of this process for high voltage applications are also clearly demonstrated.
文摘提出一种蓄电池充电控制芯片的设计,具有恒流、恒压、过压、浮充等多种不同充电模式,可以在外部微处理器的支持下针对不同种类电池和应用场合的需要实现电池的高效优化充电。讨论并给出了芯片的系统组成及主要电路的设计,在1.5μm 50 V BCD(Bipolar-CMOS-DMOS)工艺下予以实现。测试结果表明芯片工作正常,电路功能及芯片预期的主要功能已成功实现。
基金Project supported by the Young Scientists Fund of the National Natural Science Foundation of China(No.60906038)
文摘A 700 V BCD technology platform is presented for high voltage applications. An important feature is that all the devices have been realized by using a fully implanted technology in a p-type single crystal without an epitaxial or a buried layer. An economical manufacturing process, requiring only 10 masking steps, yields a broad range of MOS and bipolar components integrated on a common substrate, including 700 V nLDMOS, 200 V nLDMOS, 80 V nLDMOS, 60 V nLDMOS, 40 V nLDMOS, 700 V nJFET, and low voltage devices. A robust double RESURF nLDMOS with a breakdown voltage of 800 V and specific on-resistance of 206.2 mf2.cm2 is successfully optimized and realized. The results of this technology are low fabrication cost, simple process and small chip area for PIC products.
基金Project supported by the National Natural Science Foundation of China(No.61464002)the Science and Technology Fund of Guizhou Province(No.Qian Ke He J Zi[2014]2066)the Dr.Fund of Guizhou University(No.Gui Da Ren Ji He Zi(2013)20Hao)
文摘A new semi-insulation structure in which one isolated island is connected to the substrate was pro- posed. Based on this semi-insulation structure, an advanced BCD technology which can integrate a vertical de- vice without extra internal interconnection structure was presented. The manufacturing of the new semi-insulation structure employed multi-epitaxy and selectively multi-doping. Isolated islands are insulated with the substrate by reverse-biased PN junctions. Adjacent isolated islands are insulated by isolation wall or deep dielectric trenches. The proposed semi-insulation structure and devices fixed in it were simulated through two-dimensional numerical computer simulators. Based on the new BCD technology, a smart power integrated circuit was designed and fabri- cated. The simulated and tested results of Vertical DMOS, MOSFETs, BJTs, resistors and diodes indicated that the proposed semi-insulation structure is reasonable and the advanced BCD technology is validated.
文摘为了提高压电传感器测量系统的集成度,采用1μm高压双极—互补金属氧化物半导体—双重扩散金属氧化物半导体(BCD)工艺,设计了一种适用于压电传感器的信号调理及输出芯片。集成了电压放大型阻抗变换电路、可调增益放大电路、二线制电流输出电路。仿真结果表明:芯片具有输入阻抗高,单位增益带宽大,总增益可调范围广等特点,在12~24 V宽供电范围下可正常工作,耗电仅为3.1 m A。
