Beidou receiver based on anti-jamming antenna arrays with self-calibration for precise relative positioning

Unmanned aerial vehicles(UAVs)may be subjected to unintentional radio frequency interference(RFI)or hostile jamming attack which will lead to fail to track global navigation satellite system(GNSS)signals.Therefore,the simultaneous realization of anti-jamming and high-precision carrier phase difference positioning becomes a dilemmatic problem.In this paper,a distortionless phase digital beamforming(DBF)algorithm with self-calibration antenna arrays is proposed,which enables to obtain distortionless carrier phase while suppressing jamming.Additionally,architecture of high precision Beidou receiver based on anti-jamming antenna arrays is proposed.Finally,the performance of the algorithm is evaluated,including antenna calibration accuracy,carrier phase distortionless accuracy,and carrier phase measurement accuracy without jamming.Meanwhile,the maximal jamming to signal ratio(JSR)and real time kinematic(RTK)positioning accuracy under wideband jamming are also investigated.The experimental results based on the real-life Beidou signals show that the proposed method has an excellent performance for precise relative positioning under jamming when compared with other anti-jamming methods.

An RF frontend circuit design of a Compass and GPS dual-mode dual-channel image rejection radio receiver

This paper introduces a fully integrated low power consumption radio receiver frontend circuit for a Compass（Beidou） and GPS dual mode dual channel system with 2.5 dB NF,1.02 mm^2 areas,and 8 mA of current in 0.18μm TSMC CMOS process.Except for a few passive components for input matching,other components such as an off-chip low noise amplifier or a balun are not required.With a non-tunable passive image rejection filter,the receiver frontend can achieve around 60 dB gain and 34 dB image rejection.

A 9.8-mW 1.2-GHz CMOS frequency synthesizer with a low phase-noise LC-VCO and an I/Q frequency divider

A 1.2 GHz frequency synthesizer integrated in a RF receiver for Beidou navigation is implemented in standard 0.18μm CMOS technology.A distributed biased varactor LC voltage-controlled oscillator is employed to achieve low tuning sensitivity and optimized phase noise performance.A high-speed and low-switching-noise divider-by-2 circuit based on a source-coupled logic structure is adopted to generate a quadrature（I/Q） local oscillating signal.A high-speed 8/9 dual-modulus prescaler（DMP）,a programmable-delay phase frequency detector without dead-zone problem,and a programmable-current charge pump are also integrated into the frequency synthesizer. The frequency synthesizer demonstrates an output frequency from 1.05 to 1.30 GHz,and the phase noise is-98.53 dBc/Hz at 100-kHz offset and -121.92 dBc/Hz at 1-MHz offset from the carrier frequency of 1.21 GHz. The power dissipation of the core circuits without the output buffer is 9.8 mW from a 1.8 V power supply.The total area of the receiver is 2.4×1.6 mm^2.