An Image Encryption Method Based on Bit Plane Hiding Technology

A novel image hiding method based on the correlation analysis of bit plane is described in this paper. Firstly, based on the correlation analysis, different bit plane of a secret image is hided in different bit plane of several different open images. And then a new hiding image is acquired by a nesting ＂Exclusive-OR＂ operation on those images obtained from the first step. At last, by employing image fusion technique, the final hiding result is achieved. The experimental result shows that the method proposed in this paper is effec rive.

A Deep Convolutional Architectural Framework for Radiograph Image Processing at Bit Plane Level for Gender&Age Assessment

Assessing the age of an individual via bones serves as a fool proof method in true determination of individual skills.Several attempts are reported in the past for assessment of chronological age of an individual based on variety of discriminative features found in wrist radiograph images.The permutation and combination of these features realized satisfactory accuracies for a set of limited groups.In this paper,assessment of gender for individuals of chronological age between 1-17 years is performed using left hand wrist radiograph images.A fully automated approach is proposed for removal of noise persisted due to non-uniform illumination during the process of radiograph acquisition process.Subsequent to this a computational technique for extraction of wrist region is proposed using operations on specific bit planes of image.A framework called GeNet of deep convolutional neural network is applied for classification of extracted wrist regions into male and female.The experimentations are conducted on the datasets of Radiological Society of North America(RSNA)of about 12442 images.Efficiency of preprocessing and segmentation techniques resulted into a correlation of about 99.09%.Performance of GeNet is evaluated on the extracted wrist regions resulting into an accuracy of 82.18%.

A Reversible Data Hiding Algorithm Based on Image Camouflage and Bit-Plane Compression

Reversible data hiding in encrypted image(RDHEI)is a widely used technique for privacy protection,which has been developed in many applications that require high confidentiality,authentication and integrity.Proposed RDHEI methods do not allow high embedding rate while ensuring losslessly recover the original image.Moreover,the ciphertext form of encrypted image in RDHEI framework is easy to cause the attention of attackers.This paper proposes a reversible data hiding algorithm based on image camouflage encryption and bit plane compression.A camouflage encryption algorithm is used to transform a secret image into another meaningful target image,which can cover both secret image and encryption behavior based on“plaintext to plaintext”transformation.An edge optimization method based on prediction algorithm is designed to improve the image camouflage encryption quality.The reversible data hiding based bit-plane level compression,which can improve the redundancy of the bit plane by Gray coding,is used to embed watermark in the camouflage image.The experimental results also show the superior performance of the method in terms of embedding capacity and image quality.

High performance word level sequential and parallel coding methods and architectures for bit plane coding

This paper introduced a novel high performance algorithm and VLSI architectures for achieving bit plane coding （BPC） in word level sequential and parallel mode. The proposed BPC algorithm adopts the techniques of coding pass prediction and parallel ＆ pipeline to reduce the number of accessing memory and to increase the ability of concurrently processing of the system, where all the coefficient bits of a code block could be coded by only one scan. A new parallel bit plane architecture （PA） was proposed to achieve word-level sequential coding. Moreover, an efficient high-speed architecture （HA） was presented to achieve multi-word parallel coding. Compared to the state of the art, the proposed PA could reduce the hardware cost more efficiently, though the throughput retains one coefficient coded per clock. While the proposed HA could perform coding for 4 coefficients belonging to a stripe column at one intra-clock cycle, so that coding for an NxN code-block could be completed in approximate N2/4 intra-clock cycles. Theoretical analysis and experimental results demonstrate that the proposed designs have high throughput rate with good performance in terms of speedup to cost, which can be good alternatives for low power applications.