As the device size decreases, the soft error induced by space ions is becoming a great concern for the reliability of integrated circuits（ICs）. At present, the body biasing technique is widely used in highly scaled ...As the device size decreases, the soft error induced by space ions is becoming a great concern for the reliability of integrated circuits（ICs）. At present, the body biasing technique is widely used in highly scaled technologies. In the paper, using the three-dimensional technology computer-aided design（TCAD） simulation, we analyze the effect of the body biasing on the single-event charge collection in deep N-well technology. Our simulation results show that the body biasing mainly affects the behavior of the source, and the effect of body biasing on the charge collection for the nMOSFET and pMOSFET is quite different. For the nMOSFET, the RBB will increase the charge collection, while the FBB will reduce the charge collection. For the pMOSFET, the effect of RBB on the SET pulse width is small, while the FBB has an adverse effect. Moreover, the differenceof the effect of body biasing on the charge collection is compared in deep N-well and twin well.展开更多
A modified four transistor （4T） self-body-bias structured SRAM/SOI memory cell is proposed. The structure is designed and its parameters are obtained by performance simulation and analysis with TSUPREM4 and MEDICI.T...A modified four transistor （4T） self-body-bias structured SRAM/SOI memory cell is proposed. The structure is designed and its parameters are obtained by performance simulation and analysis with TSUPREM4 and MEDICI.The structure saves area and its process is simplified by using the body resistor with buried p^＋ channel beneath the nMOS gate instead of the pMOS of 6T CMOS SRAM. Furthermore, this structure can operate safely with a 0.5V supply voltage, which may be prevalent in the near future. Finally, compared to conventional 6T CMOS SRAM,this structure＇s transient responses are normal and its power dissipation is 10 times smaller.展开更多
This paper presents a method to reduce the energy consumption of multi-core systems characterized by processor cores and buses with discrete frequency levels under timing constraints.The proposed method takes the tran...This paper presents a method to reduce the energy consumption of multi-core systems characterized by processor cores and buses with discrete frequency levels under timing constraints.The proposed method takes the transformations of the original task graphs,which include dependent tasks located in different iterations,as inputs.The proposed method utilizes mapping selection as well as joint processor and communication frequency scaling to implement energy reduction.We conduct experiments on several random task graphs.Experimental results show that the proposed method can achieve substantial energy reduction compared with previous work under the same hard timing constraints.展开更多
文摘As the device size decreases, the soft error induced by space ions is becoming a great concern for the reliability of integrated circuits（ICs）. At present, the body biasing technique is widely used in highly scaled technologies. In the paper, using the three-dimensional technology computer-aided design（TCAD） simulation, we analyze the effect of the body biasing on the single-event charge collection in deep N-well technology. Our simulation results show that the body biasing mainly affects the behavior of the source, and the effect of body biasing on the charge collection for the nMOSFET and pMOSFET is quite different. For the nMOSFET, the RBB will increase the charge collection, while the FBB will reduce the charge collection. For the pMOSFET, the effect of RBB on the SET pulse width is small, while the FBB has an adverse effect. Moreover, the differenceof the effect of body biasing on the charge collection is compared in deep N-well and twin well.
文摘A modified four transistor （4T） self-body-bias structured SRAM/SOI memory cell is proposed. The structure is designed and its parameters are obtained by performance simulation and analysis with TSUPREM4 and MEDICI.The structure saves area and its process is simplified by using the body resistor with buried p^＋ channel beneath the nMOS gate instead of the pMOS of 6T CMOS SRAM. Furthermore, this structure can operate safely with a 0.5V supply voltage, which may be prevalent in the near future. Finally, compared to conventional 6T CMOS SRAM,this structure＇s transient responses are normal and its power dissipation is 10 times smaller.
文摘This paper presents a method to reduce the energy consumption of multi-core systems characterized by processor cores and buses with discrete frequency levels under timing constraints.The proposed method takes the transformations of the original task graphs,which include dependent tasks located in different iterations,as inputs.The proposed method utilizes mapping selection as well as joint processor and communication frequency scaling to implement energy reduction.We conduct experiments on several random task graphs.Experimental results show that the proposed method can achieve substantial energy reduction compared with previous work under the same hard timing constraints.
