At supercritical conditions a porous strip （or slot strip） placed beneath a shock wave can reduce the drag by a weaker lambda shock system, and increase the buffet boundary, even may increase the lift. Passive shock...At supercritical conditions a porous strip （or slot strip） placed beneath a shock wave can reduce the drag by a weaker lambda shock system, and increase the buffet boundary, even may increase the lift. Passive shock wave/boundary layer control （PSBC） for drag reduction was conducted by SC（2）-0714 supercritical wing, with emphases on parameter of porous/slot and bump, such as porous distribution, hole diameter, cavity depth, porous direction and so on. A sequential quadratic programming （SQP） optimization method coupled with ad]oint method was adopted to achieve the optimized shape and position of the bumps. Computational fluid dynamics （CFD）, force test and oil test with half model all indicate that PSBC with porous, slot and bump generally reduce the drag by weaker lambda shock at supercritical conditions. According to wind tunnel test results for angle of attack of 2° at Mach number M = 0.8, the porous configuration with 6.21% porosity results in a drag reduction of 0.0002 and lift-drag ratio increase of 0.2, the small bump configuration results in a drag reduction of 0.0007 and lift-drag ratio increase of 0.3. Bump normally reduce drag at design point with shock wave position being accurately computed. If bump diverges from the position of shock wave, drag will not be easily reduced.展开更多
The IEEE Standard 1149.1 boundary scan (BS) implementation provides the internal access required for testing the digital printed circuit board (PCB). However, the integrity of the boundary scan test infrastructure sh...The IEEE Standard 1149.1 boundary scan (BS) implementation provides the internal access required for testing the digital printed circuit board (PCB). However, the integrity of the boundary scan test infrastructure should be tested first to guarantee the validation of the results of the rest functional test and diagnosis. This paper describes the fault models and test principles of the BS test access port (TAP) lines on PCBs. A test algorithm with high fault coverage and short time is then presented for the PCB on which all ICs are BS ones.展开更多
文摘At supercritical conditions a porous strip （or slot strip） placed beneath a shock wave can reduce the drag by a weaker lambda shock system, and increase the buffet boundary, even may increase the lift. Passive shock wave/boundary layer control （PSBC） for drag reduction was conducted by SC（2）-0714 supercritical wing, with emphases on parameter of porous/slot and bump, such as porous distribution, hole diameter, cavity depth, porous direction and so on. A sequential quadratic programming （SQP） optimization method coupled with ad]oint method was adopted to achieve the optimized shape and position of the bumps. Computational fluid dynamics （CFD）, force test and oil test with half model all indicate that PSBC with porous, slot and bump generally reduce the drag by weaker lambda shock at supercritical conditions. According to wind tunnel test results for angle of attack of 2° at Mach number M = 0.8, the porous configuration with 6.21% porosity results in a drag reduction of 0.0002 and lift-drag ratio increase of 0.2, the small bump configuration results in a drag reduction of 0.0007 and lift-drag ratio increase of 0.3. Bump normally reduce drag at design point with shock wave position being accurately computed. If bump diverges from the position of shock wave, drag will not be easily reduced.
文摘The IEEE Standard 1149.1 boundary scan (BS) implementation provides the internal access required for testing the digital printed circuit board (PCB). However, the integrity of the boundary scan test infrastructure should be tested first to guarantee the validation of the results of the rest functional test and diagnosis. This paper describes the fault models and test principles of the BS test access port (TAP) lines on PCBs. A test algorithm with high fault coverage and short time is then presented for the PCB on which all ICs are BS ones.
