Low overhead design-for-testability for scan-based delay fault testing

An efficient design-for-testability （DFT） technique is proposed to achieve low overhead for scan-based delay fault testing. Existing techniques for delay test such as skewed-load or broadside make the test generation process complex and produce lower coverage for scan-based designs as compared with non-scan designs, whereas techniques such as enhanced-scan test can make the test easy but need an extra holding latch to add substantial hardware overhead. A new tri-state holding logic is presented to replace the common holding latch in enhanced-scan test to get a substantial low hardware overhead. This scheme can achieve low delay overhead by avoiding the holding latch on the critical timing scan path. What＇s more, this method can also keep the state and signal activity in the combinational circuit from the scan during data scan-in operation to reduce the power dissipation. Experiment results on a set of ISCAS89 benchmarks show the efficiency of the proposed scheme.

A Non-Scan Testable Design of Sequential Circuits by Improving Controllability

As a method for testing a sequential circuit efficiently, a scan design is usually used. But, since this design has some drawbacks, a non-scan testable design should be discussed. The testable design can be implemented by enhancing controllability and observability. This paper discusses a non-scan testable design for a sequential circuit by only focusing the improvement of controllability. The proposed design modifies a circuit so that all the FFs can be directly controlled by primary input lines in a test mode. Experimental results show that we can get a good testability using this method.

Compact-Parity Testing and Testable Design

Parity testing is one of the compact testing techniques, which, traditionally, relies on applying all 2^n input combinations to an n-input combinational circuit without need of knowing the implementation of the circuits under test. The faults can be detected just by observing and comparing its parity of whole output of circuit with the expectation one. The way seemed to be less interesting to the test eagineers in the past days, mainly due to the reasons of its exhaustive testing and time-cousuming, which became a barrier as the number of input lines gets growing. However its great facility and convenience in testing still interest to the engineers who need to have a quick look at the qualities of the circuits without generating the test patterns for a given circuit to be tested. In this paper, a new approach called pseudo-parity testing is presented to deal with the dilemma we are facing： i. e. to change an exhaustive parity testing into a non-exhaustive one, followed by a pseudo- parity testable design to help realize the new way of pseudo-parity testing. The idea of pseudo-parity testing presented in this paper may resume its spirits towards its promising future.

Metric Based Testability Estimation Model for Object Oriented Design: Quality Perspective

The quality factor of class diagram is critical because it has significant influence on overall quality of the product, delivered finally. Testability has been recognized as a key factor to software quality. Estimating testability at design stage is a criterion of crucial significance for software designers to make the design more testable. Taking view of this fact, this paper identifies testability factors namely effectiveness and reusability and establishes the correlation among testability, effectiveness and reusability and justifies the correlation with the help of statistical measures. Moreover study developed metric based testability estimation model and developed model has been validated using experimental test. Subsequently, research integrates the empirical validation of the developed model for high level acceptance. Finally a hypothesis test performs by the two standards to test the significance of correlation.

Quantifying Reusability of Object Oriented Design: A Testability Perspective

The quality factor of class diagram is critical because it has a significant influence on overall quality of the product, delivered finally. Testability analysis, when done early in the software creation process, is a criterion of critical importance to software quality. Reusability is an important quality factor to testability. Its early measurement in object oriented software especially at design phase, allows a design to be reapplied to a new problem without much extra effort. This research paper proposes a research framework for quantification process and does an extensive review on reusability of object oriented software. A metrics based model “Reusability Quantification of Object Oriented Design” has been proposed by establishing the relationship among design properties and reusability and justifying the correlation with the help of statistical measures. Also, “Reusability Quantification Model” is empirically validated and contextual significance of the study shows the high correlation for model acceptance. This research paper facilitates to software developers and designer, the inclusion of reusability quantification model to access and quantify software reusability for quality product.

Testable Design and BIST Techniques for Systolic Motion Estimators in Transform Domain

Testable design techniques for systolic motion estimators based on M-testability conditions are proposed in this paper. The whole motion estimator can be viewed as a two-dimensional iterative logic array （ILA） of processing elements （PEs） and multiplying elements （MULs）. The functions of each PE and MUL are modified to be bijective to meet the M-testable conditions. The number of test patterns is 2^w, where w denotes the word length of a PE. The proposed testable design techniques are also suitable for built-in self-test implementation. According to experimental results, our approaches can achieve 99.27 % fault coverage. The area overhead is about 9 %. To verify our approaches, an experimental chip is also implemented.

复杂系统测试性设计与故障诊断策略研究进展

测试性设计是提高系统可靠性、安全性、维修性、保障性的重要前沿技术,决定了系统故障检测率和隔离率,直接影响系统的维护(测试)成本。系统测试性设计包含结构化设计、模型化设计、数据驱动设计等多种设计策略。其中,数据驱动设计于近年逐渐兴起并成为重要发展方向之一,该类方法通过对系统测试与故障之间的关系进行建模,依据测试结果进行故障推理,形成故障诊断方案。首先,简要回顾了系统测试性设计的发展历程;其次,重点介绍了测试性设计的研究进展,分析总结了结构化、模型化、数据驱动3类测试方案;然后,介绍了测试性诊断策略构建,根据测试方案中的建模方法确定诊断策略的构建技术,并总结归纳了每类技术的研究特点和适用性;最后,探讨了当前复杂系统测试性设计面临的挑战性问题和可能的未来研究方向。

基于混合扫描的碳足迹采集终端可测性设计及融合诊断

在“双碳”战略的背景下,针对国内对碳足迹采集终端及系统的迫切需求,提出了基于电力采集终端及通信系统的解决方案,并利用混合边界扫描技术提出了具体的“虚拟探针”可测性设计方案。还针对基于单一类型故障特征进行非线性“簇”电路故障诊断准确率低的难题,在研究小波包变换、PCA及Volterra核特征提取的基础上,提出了小波包变换与PCA特征层融合,并与基于Volterra核特征的初级诊断结果进行决策层融合的故障诊断方法。实验表明,该方法可以有效提高故障诊断的准确率。

芯粒互连测试向量生成与测试方法研究

基于芯粒的2.5D和3D集成系统产品都具有大量的芯粒间互连,不可避免地会出现各种制造缺陷,互连测试对于提高2.5D和3D集成系统产品规模生产过程中的质量和产量至关重要。在研究传统的I-ATPG和真/补测试算法等互连测试方法的基础上提出了一种新的代码字编码方法,只需要4个代码字即可对所有矩形网络和六角网络进行代码字编码。设计了一种基于IEEE1838标准的芯粒集成系统测试架构,给出了一种典型的双芯粒互连电路并进行了测试和仿真验证,以系统性地介绍芯粒间互连测试技术。

基于合并时钟域的片上时钟描述优化方法

多时钟域的可测试性设计有两种描述片上时钟(On Chip Clock,OCC)行为的方法:时钟控制定义(Clock Control Definition,CCD)和命名捕获过程(Named Capture Procedure,NCP)。但这两种方法都存在不足:CCD无法定义复杂的时钟方案和捕获方案;NCP所需的测试向量数目多,运行时间久。有鉴于此,提出了一种合并时钟域NCP方法。合并时钟域NCP提高了对时钟、捕获方案、流程的可控性,弥补了CCD不可控的不足。实验数据表明,合并时钟域NCP在不影响覆盖率的情况下,为固定型故障(Stuck At Fault,SAF)节省约28%的测试向量数量和22%的运行时间,为跳变延迟型故障(Transition Delay Fault,TDF)节省约18%的测试向量数量和13%的运行时间,提升了测试向量的效率,弥补了NCP的不足。

装备可用性建模与优化设计方法研究

针对目前行业内缺少关于装备可用性建模与优化设计方法方面的研究成果这一问题,提出一种装备可用性建模与优化设计方法。通过可靠性、测试性、维修性和保障性信息提取,获得装备可用性设计方案的关键设计指标;建立面向多任务的装备可用性模型,并基于该模型完成装备在不同任务工作模式下的优化分析;确定装备可用性设计方案优选的多个决策属性,建立基于多属性决策的装备可用性设计方案优选模型,并基于该模型优选出装备可用性设计方案;通过案例分析验证所提方法的合理性和有效性,为装备可用性优化设计工作提供依据。

SoC芯片扫描链测试设计与实现

阐述针对SoC芯片,进行压缩测试、stuck-at测试和全速测试的设计,并通过Tessent软件插入扫描链和生成ATPG自动测试向量。结果表明,芯片固定型故障、时延相关故障的覆盖率满足测试要求。

Study of testability measurement method for equipment based on Bayesian network model

To analyze and evaluate the testability design of equipment, a testability analysis method based on Bayesian network inference model is proposed in the paper. The model can adequately apply testability information and many uncertainty information of design and maintenance process, so it can analyze testability by and large from Bayesian inference. The detailed procedure to analyze and evaluate testability for equipments by Bayesian network is given in the paper. Its modeling process is simple, its formulation is visual, and the analysis results are more reliable than others. Examples prove that the analysis method based on Bayesian network inference can be applied to testability analysis and evaluation for complex equipments.

Ethernet Controller SoC Design and Its Low-Power DFT Considerations

In this paper, an Ethernet controller SoC solution and its low power design for testability （DFT） for information appliances are presented. On a single chip, an enhanced one-cycle 8-bit micro controller unit （MCU）, media access control （MAC） circuit and embedded memories such as static random access memory （SRAM）, read only memory （ROM） and flash are all integrated together. In order to achieve high fault coverage, at the same time with low test power, different DFT techniques are adopted for different circuits： the scan circuit that reduces switching activity is implemented for digital logic circuits; BIST-based method is employed for the on-chip SRAM and ROM. According to the fault-modeling of embedded flash, we resort to a March-like method for flash built in self test （BIST）. By all means above, the result shows that the fault coverage may reach 97%, and the SoC chip is implemented successfully by using 0.25 μm two-poly four-metal mixed signal complementary metal oxide semiconductor （CMOS） technology, the die area is 4.8×4.6 mm^2. Test results show that the maximum throughput of Ethemet packets may reach 7Mb·s^1.

Failure Mode Effects and Criticality Analysis Method of Armored Equipment Based on Testability Growth

In view of the low level testability of armored equipment,the important significance of armored equipment testability growth is discussed in this paper.The failure mode effects and criticality analysis( FMECA) method to realize testability growth is introduced.Centering on the testability growth demands of new armored equipment,the deficiencies of traditional FMECA are analyzed.And an enhanced FMECA( EFMECA) method is proposed.The method increases the analysis contents,combines the information before the failure occurrence and impending failure modes together organically.Then the failure symptoms is analyzed,the failure modes and effects is determined,and the state development trend is predicted.Finally,the application of EFMECA method is illustrated by the example of the failure mode of typical armored equipment engine.

A Non-scan DFT Method at RTL Based on Fixed-control Testability to Achieve 100%Fault Efficiency

This paper proposes a non-scan design-for-testability method for register-transfer level circuits where a circuit consists of a controller and a data path. It achieves complete fault efficiency with low hardware overhead and at-speed testing.

A DFT Method for Single-Control Testability of RTL Data Paths for BIST

This paper presents a new BIST method for RTL data paths based on single-control testability, a new concept of testability. The BIST method adopts hierarchical test. Test pattern generators are placed only on primary inputs and test patterns are propagated to and fed into each module. Test responses are similarly propagated to response analyzers placed only on primary outputs. For the propagation of test patterns and test responses paths existing in the data path are utilized. The DFT method for the single-control testability is also proposed. The advantages of the proposed method are high fault coverage (for single Stuck-at faults), low hardware overhead and capability of at-speed test. Moreover, test patterns generated by test pattern generators can be fed into each module at consecutive system clocks, and thus, the BIST can also detect some faults of other fault models (e.g., transition faults and delay faults) that require consecutive application of test patterns at speed of system clock.

Testability Models for Object-Oriented Frameworks

Frameworks are time-tested highly reusable architectural skeleton structures. They are designed ‘abstract’ and ‘inco- mplete’ and are designed with predefined points of variability, known as hot spots, to be customized later at the time of framework reuse. Frameworks are reusable entities thus demand stricter and rigorous testing in comparison to one- time use application. The overall cost of framework development may be reduced by designing frameworks with high testability. This paper aims at discussing a few metric models for testability analysis of object-oriented frameworks in an attempt to having quantitative data on testability to be used to plan and monitor framework testing activities so that the framework testing effort and hence the overall framework development effort may be brought down.

An Application of Paraconsistent Annotated Logic for Design Software Testing Strategies

Nowadays, application model systems for decision-making based on non-classical logic such as Paraconsistent Logic are used successfully in the treatment of uncertainties. The method presented in this paper is based on the fundamental concepts of Paraconsistent Annotated Logic with annotation of 2 values (PAL2v). In this study, two algorithms based on PAL2v are presented gradually, to extract the effects of the contradiction in signals of information from a database of uncertain knowledge. The Paraconsistent Extractors Algorithms of Contradiction Effect-Para Extrctr is applied to filters of networks of analyses (PANets) of signal information, where uncertain and contradictory signals may be found. Software test case scenarios are subordinated to an application model of Paraconsistent decision-making, which provides an analysis using Paraconsistent Logic in the treatment of uncertainties for design software testing strategies. This quality-quantity criterion to evaluate the software product quality is based on the characteristics of software testability analysis. The Para consistent reasoning application model system presented in this case study, reveals itself to be more efficient than the traditional methods because it has the potential to offer an appropriate treatment to different originally contradicting source information.

基于MBSE的微波统一测控系统测试性设计

针对当前微波统一测控系统研制中存在的测试性要求宽松、测试性设计模式落后的问题,通过综合权衡可靠性、维修性和保障性的各项要求和约束条件,确定了微波统一测控系统的测试性定量要求,并对开展测试性定量设计和验证的可行性进行了论证;采用系统工程设计思想,将测试性设计和功能设计融合,构建了基于模型的系统工程(Model-based Systems Engineering,MBSE)的测试性设计环境和设计流程,可为微波统一测控系统在数字化研制过程中开展测试性设计和仿真验证提供参考。