An Adaptive Ramp Generator for ADC Built-in Self-Test

An adaptive ramp generator based on linear histogram was proposed for the built-in selftest (BIST) of analog to digital convertor (ADC) in CMOS image sensor. By comparing the generated ramp signal to a reference voltage and feeding back a calibration signal, the slope adjustment was implemented, and high linearity and precision of ramp slope were realized. By modulating the pulse width and reference voltage, sweep length varied from microsecond to second and signal swing could reach 3 V with 5.6 mW power consumption. The ramp was used as input to an ideal 10-bit single-slope ADC, and the corresponding DNL and INL were 0.032 LSB and 0.078 LSB, re-spectively.

A vector inserting TPG for BIST design with low peak power consumption

A test pattern generator （TPG） which can highly reduce the peak power consumption during built-in self-test （BIST） application is proposed. The proposed TPG, called LPpe-TPG, consists of a linear feedback shift register （LFSR） and some control circuits. A procedure is presented firstly to make compare vectors between pseudorandom test patterns by adding some circuits to the original LFSR and secondly to insert some vectors between two successive pseudorandom test patterns according to the ordinal selection of every two bits of the compare vector. Then the changes between any successive test patterns of the test set generated by the LPpe-TPG are not more than twice. This leads to a decrease of the weighted switching activity （WSA） of the circuit under test （CUT） and therefore a reduction of the power consumption. Experimental results based on some ISCAS＇ 85 benchmark circuits show that the peak power consumption has been reduced by 25.25% to 64.46%. Also, the effectiveness of our approach to reduce the total and average power consumption is kept, without losing stuck-at fault coverage.

An LFSR-based address generator using optimized address partition for low power memory BIST

Power consumption in test mode is much higher than that in normal mode,which is prone to causing circuit damage and reducing the yield of chips.To reduce the power dissipation efficiently,a modified linear feedback shift register(LFSR)is designed to decrease switching activity dramatically during the generation of address sequences for memory built-in self-test(MBIST).The address models are generated by a blend of two address generators with an optimized address partition and two distinct controlled clock signals.An address generator circuit for MBIST of 64 k×32 static random access memory(SRAM)is designed to illustrate the proposed scheme.Experimental results show that when the address bus size is 16 bits,compared with the traditional LFSR,the proposed LFSR can reduce the switching activity and dynamic power by 71.1%and 68.2%,respectively,with low area overhead.

A DFT Method for Single-Control Testability of RTL Data Paths for BIST

This paper presents a new BIST method for RTL data paths based on single-control testability, a new concept of testability. The BIST method adopts hierarchical test. Test pattern generators are placed only on primary inputs and test patterns are propagated to and fed into each module. Test responses are similarly propagated to response analyzers placed only on primary outputs. For the propagation of test patterns and test responses paths existing in the data path are utilized. The DFT method for the single-control testability is also proposed. The advantages of the proposed method are high fault coverage (for single Stuck-at faults), low hardware overhead and capability of at-speed test. Moreover, test patterns generated by test pattern generators can be fed into each module at consecutive system clocks, and thus, the BIST can also detect some faults of other fault models (e.g., transition faults and delay faults) that require consecutive application of test patterns at speed of system clock.

Low Cost BIST Scheme Using LFSR-RC Reseeding

A novel BIST scheme for reducing the test storage( TS) is presented. The proposed approach relies on a two-dimensional compression scheme,which combines the advantages of the previous LFSR reseeding scheme and test set embedding technique based on ring counters( RCs) to improve the encoding efficiency. It presents a general method to determine the probability of encoding as a function of the number of specified bits in the test cube,the length of the LFSR and the width of the test set,and conclude that the probability of encoding a n-bit test cube with s specified bits using a( smax+ 1 + 20 / n)-stage LFSR with a fixed polynomial is1- 10-6. Experimental results for the ISCAS '89 benchmark circuits show that compared with the previous schemes,the proposed scheme based on LFSR-RC reseeding requires 57% less TS and 99. 1% test application time( TAT) with simple and uniform BIST control logic.

A Novel BIST Approach for Testing Input/Output Buffers in SoCs

A novel built-in self-test （BIST） approach to test the configurable input/output buffers in Xilinx Virtex series SoCs （system on a chip） using hard macro has been proposed in this paper. The proposed approach can completely detect single and multiple stuck-at gate-level faults as well as associated routing resources in I/O buffers. The proposed BIST architecture has been implemented and verified on Xilinx Virtex series FPGAs （field programmable gate configurations are required array）. Only total of 10 to completely test the I/O buffers of Virtex devices.

Testable Design and BIST Techniques for Systolic Motion Estimators in Transform Domain

Testable design techniques for systolic motion estimators based on M-testability conditions are proposed in this paper. The whole motion estimator can be viewed as a two-dimensional iterative logic array （ILA） of processing elements （PEs） and multiplying elements （MULs）. The functions of each PE and MUL are modified to be bijective to meet the M-testable conditions. The number of test patterns is 2^w, where w denotes the word length of a PE. The proposed testable design techniques are also suitable for built-in self-test implementation. According to experimental results, our approaches can achieve 99.27 % fault coverage. The area overhead is about 9 %. To verify our approaches, an experimental chip is also implemented.

ON SHORTENING TEST SEQUENCE LENGTH FOR SIGNATURE ANALYZER

Based on the built-in self-test for logic circuit, a new approach is proposed to reduce pseudorandom test length. After finding worst faults in the circuit and creating their circuit models the output signals of these models will be compressed by linear feedback shift register. The test length for the worst faults can be obtained by analyzing compressed signature . Finally, using the relation between input probability and test length, we propose a new algorithm to shorten the test sequence length. So the optimum input probability and the shortest test length can be received.

Test access to deeply embedded analog terminals within an A/MS SoC

This paper presents a standard scalable and reconfigurable design for testability (SR DfT) in order to increase ac- cessibility to deeply embedded A/MS cores and to limit application of costly off-chip mixed-signal testers. SR DfT is an oscilla- tion-based wrapper compatible with digital embedded core-based SoC test methodologies. The impact of the optimized oscilla- tion-based wrapper design on MS SoC testing is evaluated in two directions: area and test time. Experimental results are presented for several SoCs from the ITC’02 test benchmarks with inclusion of eight analog filters.

AVAILABILITY MODEL FOR SELF TEST AND REPAIR IN FAULT TOLERANT FPGA-BASED SYSTEMS

Dynamically reconfigurable Field Programmable Gate Array(dr-FPGA) based electronic systems on board mission-critical systems are highly susceptible to radiation induced hazards that may lead to faults in the logic or in the configuration memory. The aim of our research is to characterize self-test and repair processes in Fault Tolerant(FT) dr-FPGA systems in the presence of environmental faults and explore their interrelationships. We develop a Continuous Time Markov Chain(CTMC) model that captures the high level fail-repair processes on a dr-FPGA with periodic online Built-In Self-Test(BIST) and scrubbing to detect and repair faults with minimum latency. Simulation results reveal that given an average fault interval of 36 s, an optimum self-test interval of 48.3 s drives the system to spend 13% of its time in self-tests, remain in safe working states for 76% of its time and face risky fault-prone states for only 7% of its time. Further, we demonstrate that a well-tuned repair strategy boosts overall system availability, minimizes the occurrence of unsafe states, and accommodates a larger range of fault rates within which the system availability remains stable within 10% of its maximum level.

Fault Detection and Test Response Compaction with Array of Two-Input Linear Logic

The design of space-efficient support hardware for built-in self-testing is of great significance in very large scale integration circuits and systems, particularly in view of the paradigm shift in recent times from system-on-board to system-on-chip technology. The subject paper proposes a new approach to designing aliasing-free or zero-aliasing space compaction hardware targeting specifically embedded cores-based system-on-chips for single stuck-line faults extending well-known concept from conventional switching theory, viz. that of compatibility relation as used in the minimization of incomplete sequential machines. For a pair of response outputs of the circuit under test, the method introduces the notion of fault detection compatibility and conditional fault detection compatibility （conditional upon some other response output pair being simultaneously fault detection compatible） with respect to two-input XOR/XNOR logic. The process is illustrated with design details of space compressors for the International Symposium on Circuits and Systems or ISCAS 85 combinational and ISCAS 89 full-scan sequential benchmark circuits using simulation programs ATALANTA and FSIM, attesting to the usefulness of the technique for its relative simplicity, resultant low area overhead and full fault coverage for single stuck-line faults, thus making it suitable in commercial design environments.

High Level Synthesis for Loop-Based BIST

Area and test time are two major overheads encountered duringdata path high level synthesis for BIST. This paper presents an approach to behavioral synthesis for loop-based BIST. By taking into account the requirements of theBIST scheme during behavioral synthesis processes, an area optimal BIST solutioncan be obtained. This approach is based on the use of test resources reusabilitythat results in a fewer number of registers being modified to be test registers. Thisis achieved by incorporating self-testability constraints during register assignmentoperations. Experimental results on benchmarks are presented to demonstrate theeffectiveness of the approach.

Test Time Minimization for Hybrid BIST of Core-Based Systems

This paper presents a solution to the test time minimization problem for core-based systems. We assume a hybrid BIST approach, where a test set is assembled, for each core, from pseudorandom test patterns that are generated online, and deterministic test patterns that are generated off-line and stored in the system. In this paper we propose an iterative algorithm to find the optimal combination of pseudorandom and deterministic test sets of the whole system, consisting of multiple cores, under given memory constraints, so that the total test time is minimized. Our approach cmploys a fast estimation methodology in order to avoid exhaustive search and to speed-up the calculation process. Experimental results have shown the efficiency of the algorithm to find near optimal solutions.

On the Input Probability for Built-in Test

in this paper ,based on the butlt-in self-test technique to logic circuil ,a nme approach is pro-posed to optimize input probability of digital circuit. After the worst faults are found and their circuitmodel are created the output signals of these models will be compressed by “1” counter. Fault detectprobabilities for the worst faults can be obtained by analyzing compact data. Finally, using the relationbetween the input probability and the fault detect probabilily ,we propose a new algorithm to optimzethe primary input probainlily of the circuit. So the shortest test length can he received.

A Loop-Based Apparatus for At-Speed Self-Testing

At-speed testing using external tester requires an expensive equipment, thus built-in self-test (BIST) is an alternative technique due to its ability to perform on-chip at-speed self-testing. The main issue in BIST for at-speed testing is to obtain high delay fault coverage with a low hardware overhead. This paper presents an improved loop-based BIST scheme, in which a configurable MISR (multiple-input signature register) is used to generate test-pair sequences. The structure and operation modes of the BIST scheme are described. The topological properties of the state-transit ion- graph of t he proposed B IS T scheme are analyzed. B ased on it, an approach to design and efficiently implement the proposed BIST scheme is developed. Experimental results on academic benchmark circuits are presented to demonstrate the effectiveness of the proposed BIST scheme as well as the design approach.

Design-for-Testability Features and Test Implementation of a Giga Hertz General Purpose Microprocessor

This paper describes the design-for-testability （DFT） features and low-cost testing solutions of a general purpose microprocessor. The optimized DFT features are presented in detail. A hybrid scan compression structure was executed and achieved compression ratio more than ten times. Memory built-in self-test （BIST） circuitries were designed with scan collars instead of bitmaps to reduce area overheads and to improve test and debug efficiency. The implemented DFT framework also utilized internal phase-locked loops （PLL） to provide complex at-speed test clock sequences. Since there are still limitations in this DFT design, the test strategies for this case are quite complex, with complicated automatic test pattern generation （ATPG） and debugging flow. The sample testing results are given in the paper. All the DFT methods discussed in the paper are prototypes for a high-volume manufacturing （HVM） DFT plan to meet high quality test goals as well as slow test power consumption and cost.

Exploiting Deterministic TPG for Path Delay Testing

Detection of path delay faults requires two-pattern tests. BIST technique provides a low-cost test solution. This paper proposes an approach to designing a cost-effective deterministic test pattern generator (TPG) for path delay testing. Given a set of pre-generated test-pairs with pre-determined fault coverage, a deterministic TPG is synthesized to apply the given test-pair set in a limited test time. To achieve this objective, configurable linear feedback shift register (LFSR) structures are used. Techniques are developed to synthesize such a TPG, which is used to generate an unordered deterministic test-pair set. The resulting TPG is very efficient in terms of hardware size and speed performance. Simulation of academic benchmark circuits has given good results when compared to alternative solutions.

Reducing test-data volume and test-power simultaneously in LFSR reseeding-based compression environment

This paper presents a new test scheme based on scan block encoding in a linear feedback shift register （LFSR） reseeding-based compression environment.Meanwhile,our paper also introduces a novel algorithm of scan-block clustering.The main contribution of this paper is a flexible test-application framework that achieves significant reductions in switching activity during scan shift and the number of specified bits that need to be generated via LFSR reseeding.Thus,it can significantly reduce the test power and test data volume.Experimental results using Mintest test set on the larger ISCAS＇89 benchmarks show that the proposed method reduces the switching activity significantly by 72%-94%and provides a best possible test compression of 74%-94%with little hardware overhead.