A New Method for Optimizing Layout Parameter ofan Integrated On-Chip Inductor in CMOSRF IC's

Analyzing the influence on Q factor, which was caused by the parasitic effect in a CMOS RF on chip integrated inductor, a concise method to increase the Q factor has been obtained when optimizing the layout parameter. Using this method, the Q factor of 7.9 can be achieved in a 5nH inductor (operating frequency is 2GHz) while the errors in inductance are less than 0.5% compared with the aimed values. It is proved by experiments that this method can guarantee the sufficient accuracy but require less computation time. Therefore, it is of great use for the design of the inductor in CMOS RF IC’s.

射频前端技术应用

在这篇文章里我们讨论了很多针对移动、无线和消费类射频前端应用的高等射频前端的系统与电路设计问题(?)在对应用趋势分析后。

A transformer-loaded receiver front end for 2.4 GHz WLAN in 0.13μm CMOS technology

A 2.4 GHz radio frequency receiver front end with an on-chip transformer compliant with IEEE 802.11b/g standards is presented. Based on zero-IF receiver architecture, the front end comprises a variable gain common-source low noise amplifier with an on-chip transformer as its load and a high linear quadrature folded Gilbert mixer. As the load of the LNA, the on-chip transformer is optimized for lowest resistive loss and highest power gain. The whole front end draws 21 mA from 1.2 V supply, and the measured results show a double side band noise figure of 3.75 dB, -31 dBm IIP3 with 44 dB conversion gain at maximum gain setting. Implemented in 0.13 μm CMOS technology, it occupies a 0.612 mm^2 die size.

A fully integrated direct-conversion digital satellite tuner in 0.18μm CMOS

A fully integrated direct-conversion digital satellite tuner for DVB-S/S2 and ABS-S applications is presented.A broadband noise-canceling Balun-LNA and passive quadrature mixers provided a high-linearity low noise RF front-end,while the synthesizer integrated the loop filter to reduce the solution cost and system debug time.Fabricated in 0.18μm CMOS,the chip achieves a less than 7.6 dB noise figure over a 900-2150 MHz L-band, while the measured sensitivity for 4.42 MS/s QPSK-3/4 mode is -91 dBm at the PCB connector.The fully integrated integer-N synthesizer operating from 2150 to 4350 MHz achieves less than 1℃integrated phase error. The chip consumes about 145 mA at a 3.3 V supply with internal integrated LDOs.

Design of an L1 band low noise single-chip GPS receiver in 0.18 μm CMOS technology

This article presents an L1 band low noise integrated global positioning system （GPS） receiver chip using 0.18 μm CMOS technology. Dual-conversion with a low-IF architecture was used for this GPS receiver. The receiver is composed of low noise amplifier （LNA）, down-conversion mixers, band pass filter, received signal strength indicator, variable gain amplifier, programmable gain amplifier, ADC, PLL frequency synthesizer and other key blocks. The receiver achieves a maximum gain of 105 dB and noise figure less than 6 dB. The variable gain amplifier （VGA） and programmable gain amplifier （PGA） provide gain control dynamic range over 50 dB. The receiver consumes less than 160 mW from a 1.8 V supply while occupying a 2.9 mm2 chip area including the ESD I/O pads.

A saw-less direct conversion long term evolution receiver with 25% duty-cycle LO in 130 nm CMOS technology

A CMOS long-term evolution(LTE) direct convert receiver that eliminates the interstage SAW filter is presented.The receiver consists of a low noise variable gain transconductance amplifier(TCA),a quadrature passive current commutating mixer with a 25%duty-cycle LO,a trans-impedance amplifier(TIA),a 7th-order Chebyshev filter and programmable gain amplifiers(PGAs).A wide dynamic gain range is allocated in the RF and analog parts.A current commutating passive mixer with a 25%duty-cycle LO improves gain,noise,and linearity. An LPF based on a Tow-Thomas biquad suppresses out-of-band interference.Fabricated in a 0.13μm CMOS process,the receiver chain achieves a 107 dB maximum voltage gain,2.7 dB DSB NF(from PAD port),-11 dBm 11P3,and>+65 dBm UP2 after calibration,96 dB dynamic control range with 1 dB steps,less than 2%error vector magnitude(EVM) from 2.3 to 2.7 GHz.The total receiver(total I Q path) draws 89 mA from a 1.2-V LDO on chip supply.

A 1.2-V CMOS front-end for LTE direct conversion SAW-less receiver

A CMOS RF front-end for the long-term evolution（LTE） direct conversion receiver is presented.With a low noise transconductance amplifier（LNA）,current commutating passive mixer and transimpedance operational amplifier（TIA）,the RF front-end structure enables high-integration,high linearity and simple frequency planning for LTE multi-band applications.Large variable gain is achieved using current-steering transconductance stages.A current commutating passive mixer with 25%duty-cycle LO improves gain,noise and linearity.A direct coupled current-input filter（DCF） is employed to suppress the out-of-band interferer.Fabricated in a 0.13-μm CMOS process,the RF front-end achieves a 45 dB conversion voltage gain,2.7 dB NF,-7 dBm IIP3,and ＋60 dBm IIP2 with calibration from 2.3 to 2.7 GHz.The total RF front end with divider draws 40 mA from a single 1.2-V supply.

A low-power monolithic CMOS transceiver for 802.11b wireless LANs

A single-chip low-power transceiver IC operating in the 2.4 GHz ISM band is presented. Designed in 0.18μm CMOS, the transceiver system employs direct-conversion architecture for both the receiver and transmitter to realize a fully integrated wireless LAN product. A sigma-delta （∑△） fractional-N frequency synthesizer provides on-chip quadrature local oscillator frequency. Measurement results show that the receiver achieves a maximum gain of 81 dB and a noise figure of 8.2 dB, the transmitter has maximum output power of -3.4 dBm and RMS EVM of 6.8%. Power dissipation of the transceiver is 74 mW in the receiving mode and 81 mW in the transmitting mode under a supply voltage of 1.8 V, including 30 mW consumed by the frequency synthesizer. The total chip area with pads is 2.7 × 4.2 mm^2.

A low power 3-5 GHz CMOS UWB receiver front-end

A novel low power RF receiver front-end for 3-5 GHz UWB is presented. Designed in the 0.13μm CMOS process, the direct conversion receiver features a wideband balun-coupled noise cancelling transconductance input stage, followed by quadrature passive mixers and transimpedance loading amplifiers. Measurement results show that the receiver achieves an input return loss below -8.5 dB across the 3.1-4.7 GHz frequency range, maximum voltage conversion gain of 27 dB, minimum noise figure of 4 dB, IIP3 of -11.5 dBm, and IIP2 of 33 dBm. Working under 1.2 V supply voltage, the receiver consumes total current of 18 mA including 10 mA by on-chip quadrature LO signal generation and buffer circuits. The chip area with pads is 1.1 × 1.5 mm^2.

A CMOS variable gain LNA for UWB receivers

A CMOS variable gain low noise amplifier （LNA） is presented for 4.24.8 GHz ultra-wideband appli- cation in accordance with Chinese standard. The design method for the wideband input matching is presented and the low noise performance of the LNA is illustrated. A three-bit digital programmable gain control circuit is exploited to achieve variable gain. The design was implemented in 0.13μm RF CMOS process, and the die occupies an area of 0.9 mm2 with ESD pads. Totally the circuit draws 18 mA DC current from 1.2 V DC supply, the LNA exhibits minimum noise figure of 2.3 dB, S（1, 1） less than -9 dB and S（2, 2） less than -10 dB. The maximum and the minimum power gains are 28.5 dB and 16 dB respectively. The tuning step of the gain is about 4 dB with four steps in all. Also the input 1 dB compression point is -10 dBm and input third order intercept point （IIP3） is -2 dBm.

Performanceanalysisofalowpowerlownoisetunablebandpassfilterformultiband RF front end

This paper presents a low power tunable active inductor and RF band pass filter suitable for multiband RF front end circuits. The active inductor circuit uses the PMOS cascode structure as the negative transconductor of a gyrator to reduce the noise voltage. Also, this structure provides possible negative resistance to reduce the inductor loss with wide inductive bandwidth and high resonance frequency. The RF band pass filter is realized using the proposed active inductor with suitable input and output buffer stages. The tuning of the center frequency for multiband operation is achieved through the controllable current source. The designed active inductor and RF band pass filter are simulated in 180 nm and 45 nm CMOS process using the Synopsys HSPICE simulation tool and their performances are compared. The parameters, such as resonance frequency, tuning capability, noise and power dissipation, are analyzed for these CMOS technologies and discussed. The design of a third order band pass filter using an active inductor is also presented.

Investigation and modeling of the avalanche effect in MOSFETs with non-uniform finger spacing

This paper investigates the effect of a non-uniform gate-finger spacing layout structure on the avalanche breakdown performance of RF CMOS technology. Compared with a standard multi-finger device with uniform gate-finger spacing, a device with non-uniform gate-finger spacing represents an improvement of 8.5% for the drain-source breakdown voltage （BVds） and of 20% for the thermally-related drain conductance. A novel compact model is proposed to accurately predict the variation of BVds with the total area of devices, which is dependent on the different finger spacing sizes. The model is verified and validated by the excellent match between the measured and simulated avalanche breakdown characteristics for a set of uniform and non-uniform gate-finger spacing arranged nMOSFETs.