A 5.4mW Low-Noise High-Gain CMOS RF Front-End Circuit for Portable GPS Receivers

This paper describes a CMOS low noise amplifier （LNA） plus the quadrature mixers intended for use in the front-end of portable global positioning system （GPS） receivers. The LNA makes use of an inductively degenerated input stage and power-constrained simultaneous noise and input matching techniques. The quadrature mixers are based on a Gil- bert cell type. The circuits are implemented in a TSMC 0.18μm RF CMOS process. Measurement results show that a voltage conversion gain of 35dB is achieved with a cascade noise and an input return loss of - 22.3dB. The fully differential figure of 2.4dB,an input ldB compression point of - 22dBm, circuits only draw 5.4mW from a 1.8V supply.

A modulator using RF CMOS T-type attenuator for TH-UWB communications

The insertion loss （IL） of a T-type attenuator is theoretically analyzed. A T-type RF （ radio frequency） CMOS （ complementary metal-oxide-semiconductor ） attenuator is designed as an on-off keying（OOK） modulator in a time-hopping ultra wide-band （TH-UWB）communication with a carrier frequency of 4 GHz. In the topology of the OOK modulator circuit, there are three parts, an oscillator with an oscillating frequency of 4 GHz, a T-type attenuator constructed by RF CMOS transistors, and an output impedance matching network with a L-type LC structure. The modulator is controlled by a time-hopping pulse position modulation（TH-PPM） signal. The envelope of the modulated signal varies with the amplitude of the controlling signal. Meanwhile, an output matching network is also designed to match a 50 Ω load. In 0. 18 μm RF CMOS technology, a modulator is designed and simulated. The implemented modulator chip has 65 mV of the output amplitude at a 50 fl load from a 1.8 V supply, and the return loss （ S11 ） at the output port is less than - 10 dB. The chip size is 0. 7 mm × 0. 8 mm, and the power consumption is 12. 3 mW.

A New Method for Optimizing Layout Parameter ofan Integrated On-Chip Inductor in CMOSRF IC's

Analyzing the influence on Q factor, which was caused by the parasitic effect in a CMOS RF on chip integrated inductor, a concise method to increase the Q factor has been obtained when optimizing the layout parameter. Using this method, the Q factor of 7.9 can be achieved in a 5nH inductor (operating frequency is 2GHz) while the errors in inductance are less than 0.5% compared with the aimed values. It is proved by experiments that this method can guarantee the sufficient accuracy but require less computation time. Therefore, it is of great use for the design of the inductor in CMOS RF IC’s.

Parameter Extraction for 2-π Equivalent Circuit Model of RF CMOS Spiral Inductors

A novel parameter extraction method with rational functions is presented for the 2-πequivalent circuit model of RF CMOS spiral inductors. The final S-parameters simulated by the circuit model closely match experimental data. The extraction strategy is straightforward and can be easily implemented as a CAD tool to model spiral inductors. The resulting circuit models will be very useful for RF circuit designers.

Current Mismatches in Charge Pumps of DLL-Based RF CMOS Oscillators

A research on the spurious tones due to the current mismatch in charge pumps of DLL(Delay Locked Loop) based RF CMOS oscillators is performed.An equation for strength evaluation of the spurious tones is derived.Two tables are provided to make it obvious to understand for the characteristics of spurious tones changing with related parameters.Some suggestions are given for the design of a DLL based RF CMOS oscillators.

The Jitter Performance Comparison Between DLL and PLL-Based RF CMOS Oscillators

By jitter performance comparison between PLL (Phase Locked Loop) and DLL (Delay Locked Loop),a helpful equation is derived for the structure choice between DLL and PLL based synthesizers fabricated in CMOS processes to get an optimum jitter performance and power consumption.For a frequency synthesizer,a large multiple factor prefers PLL based configuration which consumes less power,while a small one needs DLL based topology which produces a better jitter performance.

Optimization and Synthesis of RF CMOS Polyphase Filters with Layout Considerations

A novel software tool for optimization and synthesis of RF CMOS polyhase filters(PPFs),PPFOPTIMA,is developed.In the optimization engine,genetic algorithm is adopted to avoid local optima.Experiments on PPFOPTIMA demonstrate that it is an efficient design aid for design and optimization of RF CMOS PPFs.

A Low-Voltage,Low-Power CMOS High Dynamic Range dB-Linear VGA for Super Heterodyne Receivers

This paper presents a low-voltage low-power variable gain amplifier,which is applied in the automatic gain control loop of a super heterodyne receiver. Six stages are cascaded to provide an 81dB digitally controlled gain range in a 3dB step. The gain step error is less than 0.5dB. It operates at an intermediate frequency of 300kHz, and the power consumption is 1.35mW from a 1.8V supply. The prototype chip is implemented in a TSMC＇s 0.18μm 1P6M CMOS process and occupies approximately 0.24mm^2 . It is very suitable for portable wire- less communication systems. The measurement results agree well with the system requirements.

An Implementation of a CMOS Down-Conversion Mixer for GSM1900 Receivers

A 1.9GHz down-conversion CMOS mixer with a novel folded Gilbert cell,intended for use in GSM1900 （PCS1900） low-IF receivers,is fabricated in a RF 0.18μm CMOS process. The prototype demonstrates good performance at an intermediate frequency of 100kHz. It achieves a conversion gain of 6dB, SSB noise figure of 18. 5dB （1MHz IF） ,and IIP3 11.5dBm while consuming a 7mA current from a 3.3V power supply.

A DESIGN OF 0.25μm CMOS SWITCH

Single-Pole Double-Throw （SPDT） broadband switch has been designed in a 0.25gm Complementary Metal Oxide Semiconductor （CMOS） process. To optimize the performance of isolation and insertion loss, based on normal design, the effects of Gate Series Resistances （GSR） on insertion loss and switching time are analyzed for the first time. The compatible GSRs are chosen by the analyses. The fabricated chips were tested and the results show the switch isolation from DC （Direct Current） to 1GHz exhibits 55dB and insertion loss lower than 2.1 dB.

射频前端技术应用

在这篇文章里我们讨论了很多针对移动、无线和消费类射频前端应用的高等射频前端的系统与电路设计问题(?)在对应用趋势分析后。

One-Branch Zero-IF Wireless Receiver Topology with Multiphase Local Oscillator

This paper proposes a one-branch zero-IF receiver topology, which samples the I and Q signals of the modulated RF carrier with one signal path by means of a multiphase local oscillator. The suggested one-branch re- ceiver works without matching problem, and it is also capable of cancelling out the flicker noise and DC-offset when the local oscillator is configured to the four-phase mode. The one-branch receiver saves much area and power com- pared with the traditional two-branch ones. All of the advantages above make the one-branch receiver topology a promising architectural candidate for low-power and low-cost RF CMOS receiver designs. Keywords： RF CMOS; zero-IF; flicker noise; image rejection; low-power; IQ matching

A Low Power Dissipation Wide-Band CMOS Frequency Synthesizer for a Dual-Band GPS Receiver

This paper presents a wide tuning range CMOS frequency synthesizer for a dual-band GPS receiver,which has been fabricated in a standard 0.18μm RF CMOS process. With a high Q on-chip inductor, the wide-band VCO shows a tuning range from 2 to 3.6GHz to cover 2.45 and 3.14GHz in case of process corner or temperature variation,with a current consumption varying accordingly from 0.8 to 0.4mA,from a 1.8V supply voltage. Measurement results show that the whole frequency synthesizer consumes very low power of 5.6mW working at L1 band with in-band phase noise less than - 82dBc/Hz and out-of-band phase noise about - ll2dBc/Hz at 1MHz offset from a 3. 142GHz carrier. The performance of the frequency synthesizer meets the requirements of GPS applications very well.

A Fully-Integrated Dual Band CMOS Power Amplifier Based on an Active Matching Transformer

We propose a dual band CMOS power amplifier for mobile WiMAX systems. The power amplifier,combined with an active matching transformer,is fully integrated and fabricated in a 0.13μm CMOS process. The transformer operates at dual bands with active matching circuit. The measured result shows that the transformer efficiency of 78.2% and 70.4% at 2.5 and 3.5GHz are realized,respectively,and 26.5 and 24. 8dB gain are achieved. The PAE reaches 20% and 28% at 2.5 and 3.5GHz, respectively. The third inter-modulation （IM3） is lower than - 30dBc at the 25dBm average power.

A transformer-loaded receiver front end for 2.4 GHz WLAN in 0.13μm CMOS technology

A 2.4 GHz radio frequency receiver front end with an on-chip transformer compliant with IEEE 802.11b/g standards is presented. Based on zero-IF receiver architecture, the front end comprises a variable gain common-source low noise amplifier with an on-chip transformer as its load and a high linear quadrature folded Gilbert mixer. As the load of the LNA, the on-chip transformer is optimized for lowest resistive loss and highest power gain. The whole front end draws 21 mA from 1.2 V supply, and the measured results show a double side band noise figure of 3.75 dB, -31 dBm IIP3 with 44 dB conversion gain at maximum gain setting. Implemented in 0.13 μm CMOS technology, it occupies a 0.612 mm^2 die size.

A fully integrated direct-conversion digital satellite tuner in 0.18μm CMOS

A fully integrated direct-conversion digital satellite tuner for DVB-S/S2 and ABS-S applications is presented.A broadband noise-canceling Balun-LNA and passive quadrature mixers provided a high-linearity low noise RF front-end,while the synthesizer integrated the loop filter to reduce the solution cost and system debug time.Fabricated in 0.18μm CMOS,the chip achieves a less than 7.6 dB noise figure over a 900-2150 MHz L-band, while the measured sensitivity for 4.42 MS/s QPSK-3/4 mode is -91 dBm at the PCB connector.The fully integrated integer-N synthesizer operating from 2150 to 4350 MHz achieves less than 1℃integrated phase error. The chip consumes about 145 mA at a 3.3 V supply with internal integrated LDOs.

Design of an L1 band low noise single-chip GPS receiver in 0.18 μm CMOS technology

This article presents an L1 band low noise integrated global positioning system （GPS） receiver chip using 0.18 μm CMOS technology. Dual-conversion with a low-IF architecture was used for this GPS receiver. The receiver is composed of low noise amplifier （LNA）, down-conversion mixers, band pass filter, received signal strength indicator, variable gain amplifier, programmable gain amplifier, ADC, PLL frequency synthesizer and other key blocks. The receiver achieves a maximum gain of 105 dB and noise figure less than 6 dB. The variable gain amplifier （VGA） and programmable gain amplifier （PGA） provide gain control dynamic range over 50 dB. The receiver consumes less than 160 mW from a 1.8 V supply while occupying a 2.9 mm2 chip area including the ESD I/O pads.

A saw-less direct conversion long term evolution receiver with 25% duty-cycle LO in 130 nm CMOS technology

A CMOS long-term evolution(LTE) direct convert receiver that eliminates the interstage SAW filter is presented.The receiver consists of a low noise variable gain transconductance amplifier(TCA),a quadrature passive current commutating mixer with a 25%duty-cycle LO,a trans-impedance amplifier(TIA),a 7th-order Chebyshev filter and programmable gain amplifiers(PGAs).A wide dynamic gain range is allocated in the RF and analog parts.A current commutating passive mixer with a 25%duty-cycle LO improves gain,noise,and linearity. An LPF based on a Tow-Thomas biquad suppresses out-of-band interference.Fabricated in a 0.13μm CMOS process,the receiver chain achieves a 107 dB maximum voltage gain,2.7 dB DSB NF(from PAD port),-11 dBm 11P3,and>+65 dBm UP2 after calibration,96 dB dynamic control range with 1 dB steps,less than 2%error vector magnitude(EVM) from 2.3 to 2.7 GHz.The total receiver(total I Q path) draws 89 mA from a 1.2-V LDO on chip supply.

A 1.2-V CMOS front-end for LTE direct conversion SAW-less receiver

A CMOS RF front-end for the long-term evolution（LTE） direct conversion receiver is presented.With a low noise transconductance amplifier（LNA）,current commutating passive mixer and transimpedance operational amplifier（TIA）,the RF front-end structure enables high-integration,high linearity and simple frequency planning for LTE multi-band applications.Large variable gain is achieved using current-steering transconductance stages.A current commutating passive mixer with 25%duty-cycle LO improves gain,noise and linearity.A direct coupled current-input filter（DCF） is employed to suppress the out-of-band interferer.Fabricated in a 0.13-μm CMOS process,the RF front-end achieves a 45 dB conversion voltage gain,2.7 dB NF,-7 dBm IIP3,and ＋60 dBm IIP2 with calibration from 2.3 to 2.7 GHz.The total RF front end with divider draws 40 mA from a single 1.2-V supply.

A low-power monolithic CMOS transceiver for 802.11b wireless LANs

A single-chip low-power transceiver IC operating in the 2.4 GHz ISM band is presented. Designed in 0.18μm CMOS, the transceiver system employs direct-conversion architecture for both the receiver and transmitter to realize a fully integrated wireless LAN product. A sigma-delta （∑△） fractional-N frequency synthesizer provides on-chip quadrature local oscillator frequency. Measurement results show that the receiver achieves a maximum gain of 81 dB and a noise figure of 8.2 dB, the transmitter has maximum output power of -3.4 dBm and RMS EVM of 6.8%. Power dissipation of the transceiver is 74 mW in the receiving mode and 81 mW in the transmitting mode under a supply voltage of 1.8 V, including 30 mW consumed by the frequency synthesizer. The total chip area with pads is 2.7 × 4.2 mm^2.