Techniques for constructing metamodels of device parameters at BSIM3v3 level accuracy are presented to improve knowledge-based circuit sizing optimization. Based on the analysis of the prediction error of analytical p...Techniques for constructing metamodels of device parameters at BSIM3v3 level accuracy are presented to improve knowledge-based circuit sizing optimization. Based on the analysis of the prediction error of analytical performance expressions, operating point driven （OPD） metamodels of MOSFETs are introduced to capture the circuit＇s characteristics precisely. In the algorithm of metamodel construction, radial basis functions are adopted to interpolate the scattered multivariate data obtained from a well tailored data sampling scheme designed for MOSFETs. The OPD metamodels can be used to automatically bias the circuit at a specific DC operating point. Analytical-based performance expressions composed by the OPD metamodels show obvious improvement for most small-signal performances compared with simulation-based models. Both operating-point variables and transistor dimensions can be optimized in our nesting-loop optimization formulation to maximize design flexibility. The method is successfully applied to a low-voltage low-power amplifier.展开更多
A fully-differential switched-capacitor sample-and-hold （S/H） circuit used in a 10-bit 50-MS/s pipeline analog-to-digital converter （ADC） was designed and fabricated using a 0.35-μm CMOS process. Capacitor flip-a...A fully-differential switched-capacitor sample-and-hold （S/H） circuit used in a 10-bit 50-MS/s pipeline analog-to-digital converter （ADC） was designed and fabricated using a 0.35-μm CMOS process. Capacitor flip-around architecture was used in the S/H circuit to lower the power consumption. In addition, a gain-boosted operational transconductance amplifier （OTA） was designed with a DC gain of 94 dB and a unit gain bandwidth of 460 MHz at a phase margin of 63 degree, which matches the S/H circuit. A novel double-side bootstrapped switch was used, improving the precision of the whole circuit. The measured results have shown that the S/H circuit reaches a spurious free dynamic range （SFDR） of 67 dB and a signal-to-noise ratio （SNR） of 62.1 dB for a 2.5 MHz input signal with 50 MS/s sampling rate. The 0.12mm^2 S/H circuit operates from a 3.3 V supply and consumes 13.6 mW.展开更多
文摘Techniques for constructing metamodels of device parameters at BSIM3v3 level accuracy are presented to improve knowledge-based circuit sizing optimization. Based on the analysis of the prediction error of analytical performance expressions, operating point driven （OPD） metamodels of MOSFETs are introduced to capture the circuit＇s characteristics precisely. In the algorithm of metamodel construction, radial basis functions are adopted to interpolate the scattered multivariate data obtained from a well tailored data sampling scheme designed for MOSFETs. The OPD metamodels can be used to automatically bias the circuit at a specific DC operating point. Analytical-based performance expressions composed by the OPD metamodels show obvious improvement for most small-signal performances compared with simulation-based models. Both operating-point variables and transistor dimensions can be optimized in our nesting-loop optimization formulation to maximize design flexibility. The method is successfully applied to a low-voltage low-power amplifier.
基金supported by the National High Technology Research and Development Program of China(No.2002AA1Z1200)
文摘A fully-differential switched-capacitor sample-and-hold （S/H） circuit used in a 10-bit 50-MS/s pipeline analog-to-digital converter （ADC） was designed and fabricated using a 0.35-μm CMOS process. Capacitor flip-around architecture was used in the S/H circuit to lower the power consumption. In addition, a gain-boosted operational transconductance amplifier （OTA） was designed with a DC gain of 94 dB and a unit gain bandwidth of 460 MHz at a phase margin of 63 degree, which matches the S/H circuit. A novel double-side bootstrapped switch was used, improving the precision of the whole circuit. The measured results have shown that the S/H circuit reaches a spurious free dynamic range （SFDR） of 67 dB and a signal-to-noise ratio （SNR） of 62.1 dB for a 2.5 MHz input signal with 50 MS/s sampling rate. The 0.12mm^2 S/H circuit operates from a 3.3 V supply and consumes 13.6 mW.
