Low phase noise LC VCO design in CMOS technology

This paper presents the design and the experimental measurements of two complementary metal-oxide-semiconductor (CMOS) LC-tuned voltage controlled oscillators (VCO) implemented in a 0.18 μm 6-metal-layer mixed-signal/RF CMOS technology. The design methodologies and approaches for the optimization of the ICs are presented. The first design is optimized for mixed-signal transistor, oscillated at 2.64 GHz with a phase noise of -93.5 dBc/Hz at 500 kHz offset. The second one optimized for RF transistor, using the same architecture, oscillated at 2.61 GHz with a phase noise of -95.8 dBc/Hz at 500 kHz offset. Under a 2 V supply, the power dissipation is 8 mW, and the maximum buffered output power for mixed-signal and RF transistor are -7 dBm and -5.4 dBm, respectively. Both kinds of oscillators make use of on-chip components only, allowing for simple and robust integration.

A 12bit 300MHz Current-Steering CMOS D/A Converter

The proposed DAC consists of a unit current-cell matrix for 8MSBs and a binary-weighted array for 4LSBs,trading-off between the precision,speed,and size of the chip.In order to ensure the linearity of the DAC,a double Centro symmetric current matrix is designed by the Q2 random walk strategy.To achieve better dynamic performance,a latch is added in front of the current switch to change the input signal,such as its optimal cross-point and voltage level.For a 12bit resolution,the converter reaches an update rate of 300MHz.

200Ms/s 177mW 8bit Folding and Interpolating CMOS A/D Converter

A CMOS folding and interpolating analog-to-digital converter (ADC) for embedded application is described.The circuit is fully compatible with standard digital CMOS technology.A modified folding block implemented without resistor contributes to a small chip area.At the input stage,offset averaging reduces the input capacitance and the distributed track-and-hold circuits are proposed to improve signal-to-noise-plus-distortion ratio.The 200Ms/s 8bit ADC with 177mW total power consumption at 3.3V power supply is realized in standard digital 0.18μm 3.3V CMOS technology.

An Implementation of a CMOS Down-Conversion Mixer for GSM1900 Receivers

A 1.9GHz down-conversion CMOS mixer with a novel folded Gilbert cell,intended for use in GSM1900 （PCS1900） low-IF receivers,is fabricated in a RF 0.18μm CMOS process. The prototype demonstrates good performance at an intermediate frequency of 100kHz. It achieves a conversion gain of 6dB, SSB noise figure of 18. 5dB （1MHz IF） ,and IIP3 11.5dBm while consuming a 7mA current from a 3.3V power supply.

A 10bit 2GHz CMOS D/A Converter for High-Speed System Applications

This paper presents a 2GS/s 10bit CMOS digital-to-analog converter （DAC） that consists of two unit current-cell matrixes for 6MSBs and 4LSBs, respectively, trading off between the precision and size of the chip. Current mode logic （CML） is used to ensure high speed,and a double centro-symmetric current matrix is designed by the Q^2 random walk strategy in order to ensure the linearity of the DAC. The DAC occupies 2.2mm × 2.2mm of die area and consumes 790mW with a single 3.3V power supply.

Design, Fabrication, and Modeling of CMOS-Compatible Double Photodiode

A double photodiode (PD) constructed by p+/N-well junction and N-well/p-sub junction was designed and fabricated in a UMC 0.18-μm CMOS process. Based on the device structure and mechanism of double PD, a novel small-signal equivalent circuit model considering the carrier transit effect and the parasitic RC time constant was presented. By this model with complete electronic components, the double PD can be incorporated in a commercial circuit simulator. The component values were extracted by fitting the measured S-parameters using simulated annealing algorithm, and a good agreement between the measurement and the simulation results was achieved. © 2017, Tianjin University and Springer-Verlag Berlin Heidelberg.

Study of CMOS integrated signal processing circuit in capacitive sensors

A CMOS integrated signal processing circuit based on capacitance resonance principle whose structure is simple in capacitive sensors is designed. The waveform of output voltage is improved by choosing bootstrap reference current mirror with initiate circuit, CMOS analogy switch and positive feedback of double-stage inverter in the circuit. Output voltage of this circuit is a symmetric square wave signal. The variation of sensitive capacitance, which is part of the capacitive sensors, can be denoted by the change of output vohage＇s frequency. The whole circuit is designed with 1.5 μm P-weU CMOS process and simulated by PSpice software. Output frequency varies from 261.05 kHz to 47. 93 kHz if capacitance varies in the range of 1PF - 15PF. And the variation of frequency can be easily detected using counter or SCU.

Development of 0.50μm CMOS Integrated Circuits Technology

Submicron CMOS IC technology, including triple layer resist lithography technology, RIE, LDD, Titanium Salicide, shallow junction, thin gate oxide, no bird's beak isolation and channel's multiple implantation doping technology have been developed. 0.50μm. CMOS integrated circuits have been fabricated using this submicron CMOS process.

2.5 Gb/s 16∶1 MUX IC Design with CMOS

A low-power and high-speed 16:1 MUX IC designed for Optical fiber communication based on TSMC 0.25 μm CMOS technology is represented. A tree-type architecture was utilized. The output data bit rate is 2.5 Gb/s at input clock rate of 1.25 GHz. The simulation results show that the output signal has peak-to-peak amplitude of 400 mV, the power dissipation is less than 200 mW and the power dissipation of core circuit is less than 20 mW at the 2.5 Gb/s standard bit rate and supply voltage of 2.5 V. The chip area is （1.8） mm2.

Double-ended passivator enables dark-current-suppressed colloidal quantum dot photodiodes for CMOS-integrated infrared imagers

Lead sulfide(PbS)colloidal quantum dot(CQD)photodiodes integrated with silicon-based readout integrated circuits(ROICs)offer a promising solution for the next-generation short-wave infrared(SWIR)imaging technology.Despite their potential,large-size CQD photodiodes pose a challenge due to high dark currents resulting from surface states on nonpassivated(100)facets and trap states generated by CQD fusion.In this work,we present a novel approach to address this issue by introducing double-ended ligands that supplementally passivate(100)facets of halidecapped large-size CQDs,leading to suppressed bandtail states and reduced defect concentration.Our results demonstrate that the dark current density is highly suppressed by about an order of magnitude to 9.6 nA cm^(2) at -10 mV,which is among the lowest reported for PbS CQD photodiodes.Furthermore,the performance of the photodiodes is exemplary,yielding an external quantum efficiency of 50.8%(which corresponds to a responsivity of 0.532 A W^(-1))and a specific detectivity of 2.5×10^(12) Jones at 1300 nm.By integrating CQD photodiodes with CMOS ROICs,the CQD imager provides high-resolution(640×512)SWIR imaging for infrared penetration and material discrimination.

A Thermal-Conscious Integrated Circuit Power Model and Its Impact on Dynamic Voltage Scaling Techniques

We propose a novel thermal-conscious power model for integrated circuits that can accurately predict power and temperature under voltage scaling. Experimental results show that the leakage power consumption is underestimated by 52 % if thermal effects are omitted. Furthermore, an inconsistency arises when energy and temperature are simultaneously optimized by dynamic voltage scaling. Temperature is a limiting factor for future integrated circuits,and the thermal optimization approach can attain a temperature reduction of up to 12℃ with less than 1.8% energy penalty compared with the energy optimization one.

A CMOS Microarray with On-Chip Decoder/Amplifier and Its Integration with a Bio-Nano-System

A fully integrated CMOS bio-chip is designed in a SMIC 0.18μm CMOS mixed signal process and successfully integrated with a novel bio-nano-system. The proposed circuit integrates an array of 4 × 4 （16 pixels） of 19μm × 19μm electrodes,a counter electrode, a current mode preamplifier circuit （CMPA） ,a digital decoding circuit,and control logics on a single chip, It provides a - 1.6- 1.6V range of assembly voltage,Sbit potential resolution, and a current gain of 39.8dB with supply voltage of 1.8V. The offset and noise are smaller than 5.9nA and 25.3pArms,respectively. Experimental resuits from on-chip selective assembly of 30nm poly （ethylene glycol） （PEG） coated magnetic nano-particles （MNPs） targeted at biosensor applications are included and discussed to verify the feasibility of the proposed circuits.

A Compact Direct Digital Frequency Synthesizer for the Rubidium Atomic Frequency Standard

A compact direct digital frequency synthesizer （DDFS） for system-on-chip implementation of the high precision rubidium atomic frequency standard is developed. For small chip size and low power consumption, the phase to sine mapping data is compressed using sine symmetry technique, sine-phase difference technique, quad line approximation technique,and quantization and error read only memory （QE-ROM） technique. The ROM size is reduced by 98% using these techniques. A compact DDFS chip with 32bit phase storage depth and a 10bit on-chip digital to analog converter has been successfully implemented using a standard 0.35μm CMOS process. The core area of the DDFS is 1.6mm^2. It consumes 167mW at 3.3V,and its spurious free dynamic range is 61dB.

New battery management system for multi-cell li-ion battery packs

This paper proposes a new battery management system （BMS） based on a master-slave control mode for multi-cell li-ion battery packs. The proposed BMS can be applied in li-ion battery packs with any cell number. The whole system is composed of a master processor and a string of slave manager cells （SMCs）. Each battery cell corresponds to an SMC. Unlike the conventional BMS, the proposed one has a novel method for communication, and it collects the battery status information in a direct and simple way. An SMC communicates with its adjacent counterparts to transfer the battery information as well as the commands from the master processor. The nethermost SMC communicates with the master processor directly. This method allows the battery management chips to be implemented in a standard CMOS （ complementary metal-oxide-semiconductor transistor） process. A testing chip is fabricated in the CSMC 0.5 μm 5 V N-well CMOS process. The testing results verify that the proposed method for data communication and the battery management system can protect and manage multi-cell li-ion battery packs.

A Novel Regulation Technique and Its Application to Design of Embedded SC DC-DC Converters

An optimized design of the monolithic switched capacitor DC-DC converter is presented.The general topologic circuit and its basic operating principles are discussed theoretically.Circuit equivalent resistance regulation method is proposed as a feasible method to design the on-chip converters.N-channel MOSFETs,instead of Schottky diodes,are used as the diodes in the converters because of their processing compatibility in monolithic fabrication.One more manufacture step,however,is expected to adjust the threshold voltage of the MOSFETs for improving output characteristics of the converters.As an example,a step-up switched-capacitor converter is fabricated in a 2μm p-well double-poly single-metal CMOS technology with breakdown voltage of 15V.Test results indicate that a single sampling cell with 0.4mm 2 of die size can deliver energy up to 0.63mW at 5V output under the condition of 3V input.Efficiency of the tested sample is 68% at 9.8MHz switching frequency...

An 85mW 14-bit 150MS/s Pipelined ADC with a Merged First and Second MDAC

A low-power 14-bit 150MS/s an- alog-to-digital converter （ADC） is present- ed for communication applications. Range scaling enables a maximal 2-Vp-p input with a single-stage opamp adopted. Opamp and capacitor sharing between the first multi- plying digital-to-analog converter （MDAC） and the second one reduces the total opamp power further. The dedicated sample-and- hold amplifier （SHA） is removed to lower the power and the noise. The blind calibration of linearity errors is proposed to improve the per- formance. The prototype ADC is fabricated in a 130rim CMOS process with a 1.3-V supply voltage. The SNDR of the ADC is 71.3 dB with a 2.4 MHz input and remains 68.5 dB for a 120 MHz input. It consumes 85 roW, which includes 57 mW for the ADC core, 11 mW for the low jitter clock receiver and 17 mW for the high-speed reference buffer.

A novel low-voltage high precision current reference based on subthreshold MOSFETs

A novel topology low-voltage high precision current reference based on subthreshold Metal-Oxide-Semiconductor Field Effect Transistors （MOSFETs） is presented. The circuit achieves a temperature-independent reference current by a proper combination current of two first-order temperature-compensation current references, which exploit the temperature characteristics of integrated poly2 resistors and the 1- V transconductance characteristics of MOSFET operating in the subthreshold region. The circuit, designed with the 1 st silicon 0.35 μm standard CMOS logic process technology, exhibits a stable current of about 2.25 μA with much low temperature coefficient of 3 × 10^-4μA/℃ in the temperature range of-40-150 ℃ at 1 V supply voltage, and also achieves a better power supply rejection ratio （PSRR） over a broad frequency. The PSRR is about -78 dB at DC and remains -42 dB at the frequency higher than 10 MHz. The maximal process error is about 6,7% based on the Monte Carlo simulation. So it has good process compatibility.

Novel High PSRR Current Reference Based on Subthreshold MOSFETs

This paper takes full advantages of the I-V transconductance characteristics of metal-oxide semiconductor field effect transistor （MOSFET） operating in the subthreshold region and the enhancement pre-regulator technique with the high gain negative feedback loop. The proposed reference circuit, designed with the SMIC 0.18 μm standard complementary metal-oxide semiconductor （CMOS） logic process technology, exhibits a stable current of about 1.701 μA with much low temperature coefficient （TC） of 2.5×10^-4μA/℃ in the temperature range of-40 to 150℃ at 1.5 V supply voltage, and also achieves a best PSRR over a broad frequency. The PSRR is about - 126 dB at DC frequency and remains -92 dB at the frequency higher 100 MHz. Moreover the proposed reference circuit operates stably at the supply voltage higher 1.2 V and has good process compatibility.

Low-power Analog VLSI Implementation of Wavelet Transform

For applications requiring low-power,low-voltage and real-time,a novel analog VLSI implementation of continuous Marr wavelet transform based on CMOS log-domain integrator is proposed. Marr wavelet is approximated by a parameterized class of function and with Levenbery-Marquardt nonlinear least square method,the optimum parameters of this function are obtained. The circuits of implementating Marr wavelet transform are composed of analog filter whose impulse response is the required wavelet. The filter design is based on IFLF structure with CMOS log-domain integrators as the main building blocks. SPICE simulations indicate an excellent approximations of ideal wavelet.

A 150 mV-1.2 V Fully-Integrated DC-DC Converter for Thermal Energy Harvesting

With the increasing use of low voltage portable devices and wireless systems, energy harvesting has become an attractive approach to overcome the problems associated with battery life and power source. Among the different types of microenergy scavengers, the TEG （thermoelectric generators） are one of the most commonly used one. Unfortunately, due to the very small amount of voltage delivered by the TEG, an efficient DC/DC （direct current/direct current） conversion and power management techniques are needed. In this paper, a CMOS （complementary metal oxide semiconductor） fully-integrated DC/DC convener for energy harvesting applications is presented. The startup-voltage of the converter is about 140 mV, the output voltage exceeds 1.5 V, with a 20% power efficiency at least. The architecture for boosting such extremely low voltages is based on an ultra-low-voltage oscillator cross connected to two phase charge pump. The overall circuit does not require any external components and can be fully integrated in a standard CMOS low voltage technology. A test-chip has been designed in UMC （united microelectronics corporation） 180 nm CMOS process.