用于射频能量收集的低阈值CMOS整流电路设计

基于TSMC 180 nm工艺,设计了一款高效率低阈值整流电路。在传统差分输入交叉耦合整流电路的基础上,提出源极与衬底之间增加双PMOS对称辅助晶体管配合缓冲电容的改进结构,对整流晶体管进行阈值补偿。有效缓解了MOS管的衬底偏置效应,降低了整流电路的开启阈值电压,针对较低输入信号功率,提高了整流电路的功率转换效率(PCE)。同时将低阈值整流电路三级级联以提高输出电压。测试结果显示,在输入信号功率为-14 dBm@915 MHz时,三级级联低阈值整流电路实现了升压功能,能稳定输出1.2 V电压,峰值PCE约为71.32%。相较于传统结构,该低阈值整流电路更适合用于射频能量收集。

用于GaN CMOS集成技术的p型GaN欧姆接触研究

通过金属叠层结构、蒸发-合金工艺条件的优化调整,实现了低接触电阻率、高稳定的p型GaN欧姆接触技术,并研究分析了电极金属在合金过程中的扩散行为。测试结果显示,改进后的p型GaN欧姆接触电阻为11.9Ω·mm,比导通电阻率为3.9×10^(-5)Ω·cm^(2),同时在250℃以内的高温环境中欧姆特性不会发生退化。在此基础上,采用低损伤凹槽栅刻蚀、叠层栅介质沉积等工艺研制出增强型p沟道GaN晶体管器件,器件的阈值电压为-1.2 V(V_(GS)=VDS,IDS=10μA/mm),漏极电流密度为-5.6 mA/mm,导通电阻为665Ω·mm(V_(GS)=-8 V,V_(DS)=-2 V)。优异的p型GaN欧姆接触技术为高性能GaN p沟道器件的研制以及GaN CMOS集成技术的小型化、智能化、高速化发展奠定了重要基础。

紧凑型D波段宽带CMOS低噪声放大器

基于28-nm CMOS工艺,设计了一款工作于D波段的紧凑型、宽带低噪声放大器。该放大器由四级放大器单元级联而成,每级放大器单元均采用基于中和电容技术的差分共源极结构。输入、输出和级间阻抗匹配电路均由变压器网络实现,并且每个放大器单元的中心工作频率被交错配置在120GHz和155GHz附近以实现参差调谐带宽拓展,从而在宽带内实现了平坦的增益响应。仿真和测试结果表明,在34mW直流功耗下,该放大器在中心频率140GHz处实现了19.5dB的峰值增益和28GHz(128GHz~156GHz)的3dB工作带宽,噪声系数和输入1dB压缩点分别为7.8dB~9.2dB和-19.8dBm~-16.6dBm。芯片的核心面积仅为200μm×550μm。

面向超大面阵CMOS图像传感器的列总线自加速建立方法研究

在超大面阵CMOS图像传感器(COMS Image Sensor,CIS)中,由于像素面阵输出的列总线上存在超大的寄生电阻电容,列总线信号建立速度的主导因素发生改变,严重影响了读出速度.为了解决这一问题,本文提出了一种可应用于超大面阵CIS列并行读出机制的列总线自加速建立方法,基于电流增益增强理论,在不引入额外总线的前提下,通过对模拟信号建立过程的实时跟踪,加快列总线信号的变化过程,在列总线终端实现了自加速,将超长列总线的读出速度提升了一个数量级. 55 nm工艺下的测试与实验结果显示,采用本文提出的方法后,在亿级像素规模CIS列总线引入的寄生电容与寄生电阻分别为47 pF和20 kΩ的情况下,光电信号从像素节点到列级电路采样节点的上升建立时间由4μs缩短至790 ns,下降建立时间由22.43μs缩短至1.17μs,将亿级像素规模的CMOS图像传感器帧频提升至100帧,压缩了相关双采样的取样间隔时间,从而拓宽了噪声抑制的频率范围.本文方法实现了在保持低噪声和高速读出的同时,单列功耗仅有6.6μW.

基于130nm CMOS工艺的低功耗X波段雷达收发机

本文采用130 nm CMOS工艺设计了一个低功耗X波段收发机。发射机主要由压控振荡器(VCO)、输出缓冲器组成;接收机主要由低噪声放大器(LNA)和吉尔伯特正交混频器组成。提出的发射机采用互补交叉耦合结构VCO来降低功耗,以输出缓冲器为负载的三端口变压器通过线圈耦合实现本振、发射信号的两路功率分配和缓冲器输出阻抗匹配;接收机的LNA通过电流复用技术将有源巴伦和共源电路进行结构堆叠以共享工作电流,从而实现低功耗。后仿真结果显示,在1.2 V电压下,发射机输出峰值功率为7.1 dBm,在1 MHz频偏下相位噪声为−111.2 dBc/Hz,接收机噪声系数为6.8 dB,增益为24.8 dB,输入1 dB压缩点为−25.4 dBm,提出的收发机同时工作的功耗为100.8 mW,版图面积为1.3 mm×1.9 mm。

基于65 nm CMOS工艺的小型化高增益低噪声放大器设计

基于65 nm互补金属氧化物半导体(Complementary Metal Oxide Semiconductor,CMOS)工艺研制了一款用于X波段的小型化高增益低噪声放大器(Low Noise Amplifier,LNA).通过研究晶体管尺寸和偏置电压对噪声系数和增益性能的影响,确定了低噪声高增益情况下晶体管尺寸和偏置电压的取值.针对LNA的输入、输出和级间匹配,采用变压器匹配网络,使得LNA尺寸缩小至0.33 mm×0.73 mm,同时提高了电路的隔离度.在变压器中嵌入并联电容,降低了变压器的耦合系数.基于差分共源拓扑结构,引入中和电容技术,有效地抑制了晶体管栅-漏间寄生电容引起的米勒效应,提高了LNA的增益和稳定性.测试结果表明,在1 V电源电压下,该LNA的带内最大增益为22.9 dB,最小噪声系数为2.8 dB,功耗为49 mW.在射频收发系统中,本款LNA具有良好的应用前景.

一种CMOS毫米波双宽带可重构低噪声放大器

设计了一种双宽带毫米波低噪声放大器。该低噪声放大器可通过射频开关对无源电感重新配置,使其可以分别工作在中心频率为28 GHz和32 GHz的频段下,适用于5G毫米波通信。该可重构低噪声放大器基于55 nm CMOS工艺设计。后仿真结果表明,该可重构低噪声放大器在控制电压(V_(s))为0 V的情况下,在中心频率为28 GHz时,增益为23 dB,输入1 dB压缩点为-5.4 dBm;在-3 dB带宽26.1~32.2 GHz(6.1 GHz)内,噪声系数为4.1~4.4 dB;在V_(s)为1.2 V的情况下,在中心频率变为32 GHz时,增益为20 dB,输入1 dB压缩点为-7.5 dBm;在-3 dB带宽28~34 GHz(6 GHz)内,噪声系数为4.4~4.7 dB。芯片面积为0.70×0.55 mm^(2),在1.2 V的电源电压下功耗为25.2 mW。

A 2.4-GHz-Low-Power CMOS RF Transmitter for IEEE 802.15.4 Standard

This paper presents the experimental results of a low-power RF transmitter for 2.4-GHz-band IEEE 802.15.4 standard in 0.18-μm CMOS technology. In order to make an adaptive RF transmitter, several factors must be considered. The most important factors are performances, power consumption, output power, noise factor, and cost. The RF transmitter comprises a quadrature passive mixer, and a power amplifier. The proposed RF transmitter consumes only 10.8-mW under a supply voltage of 1.8-V.

Ultra wideband CMOS digital T-type attenuator with low phase errors

A proposed inductive-phase-compensation ultra wideband CMOS digital T-type attenuator design based on an analysis of minimising phase errors is presented in this letter.In a standard CMOS technology,the proposed attenuator is analytically demonstrated to have low phase errors due to the inductive-phase-compensation network.A design equation is inferred and a wide-band 4dB attenuation bit digital attenuator with low phase errors is designed as a test vehicle for the proposed approach.

1.0 V low voltage CMOS mixer based on voltage control load technique

A CMOS active mixer based on voltage control load technique which can operate at 1.0 V supply voltage was proposed,and its operation principle,noise and linearity analysis were also presented.Contrary to the conventional Gilbert-type mixer which is based on RF current-commutating,the load impedance in this proposed mixer is controlled by the LO signal,and it has only two stacked transistors at each branch which is suitable for low voltage applications.The mixer was designed and fabricated in 0.18 μm CMOS process for 2.4 GHz ISM band applications.With an input of 2.44 GHz RF signal and 2.442 GHz LO signal,the measurement specifications of the proposed mixer are:the conversion gain (GC) is 5.3 dB,the input-referred third-order intercept point (PIIP3) is 4.6 dBm,the input-referred 1 dB compression point (P1dB) is -7.4 dBm,and the single-sideband noise figure (NFSSB) is 21.7 dB.

基于列共用多采样技术的CMOS图像传感器读出电路设计

针对CMOS图像传感器中相关多采样(Correlated Multiple Sampling,CMS)技术在抑制噪声的同时使读出速度受影响的问题,设计了低噪声读出电路。读出电路采用列共用多采样技术,能够在不影响读出速度的情况下,抑制时域噪声和列固定模式噪声(Fixed Pattern Noise,FPN),改善CMOS图像传感器的成像质量。列共用多采样技术采用开关控制读出电路和像素的连接关系,以多列共用的读出电路对像素依次进行时序错开时间缩短的多次采样,完成所有像素量化的总时间保持不变。基于列共用多采样技术读出电路的降噪效果在110 nm的CMOS工艺下进行了仿真和验证。随着采样数M从1到4变化,读出时间没有增长,瞬态噪声仿真得到整个读出链路的输入参考噪声从123.8μV降低到60.6μV;加入列FPN进行仿真,输入参考失调电压由138μV降低到69μV。

Inductorless CMOS Low Noise Amplifier for Multiband Application in 0.1–1.2 GHz

A 0.18 μm CMOS low noise amplifier(LNA) by utilizing noise-canceling technique was designed and implemented in this paper. Current-reuse and self-bias techniques were used in the first stage to achieve input matching and reduce power consumption. The core size of the proposed CMOS LNA circuit without inductor was only 128 μm 9226 μm. The measured power gain and noise figure of the proposed LNA were 20.6 and 1.9 dB,respectively. The 3-dB bandwidth covers frequency from 0.1 to 1.2 GHz. When the chip was operated at a supply voltage of 1.8 V, it consumed 25.69 mW. The high performance of the proposed LNA makes it suitable for multistandard low-cost receiver front-ends within the above frequency range.

Obtaining low energy γ dose with CMOS sensors

A method is established for measuring low energy γ-rays dose by using CMOS sensors without any X-/γ-ray converters. Gamma-ray source of241 Am and152Eu are used to test the system. Based on gray value, an analysis method is proposed to obtain the γ-ray dose. Cumulative dose is determined by correlating the gray value to the dose readings of standard dosimeters. The relationship between gray value and the cumulative dose of γ-rays are trained by using back propagation neural network with BFGS algorithm. After comparison, it shows that BFGS algorithm trainings are suitable for different γ-ray sources under higher error condition. These indicate the feasibility of measuring low energy γ-ray dose by using common CMOS image sensors.

Hybrid phase-locked loop with fast locking time and low spur in a 0.18-μm CMOS process

We propose a novel hybrid phase-locked loop （PLL） architecture for overcoming the trade-off between fast locking time and low spur. To reduce the settling time and meanwhile suppress the reference spurs, we employ a wide-band single-path PLL and a narrow-band dual-path PLL in a transient state and a steady state, respectively, by changing the loop bandwidth according to the gain of voltage controlled oscillator （VCO） and the resister of the loop filter. The hybrid PLL is implemented in a 0.18-μm complementary metal oxide semiconductor （CMOS） process with a total die area of 1.4×0.46 mm2. The measured results exhibit a reference spur level of lower than -73 dB with a reference frequency of 10 MHz and a settling time of 20 μs with 40 MHz frequency jump at 2 GHz. The total power consumption of the hybrid PLL is less than 27 mW with a supply voltage of 1.8 V.

Design of Low Power and High Speed CMOS Comparator for A/D Converter Application

This paper presents an improved method for design of CMOS comparator based on a preamplifier-latch circuit driven by a clock. Design is intended to be implemented in Sigma-delta Analog-to-Digital Converter (ADC). The main advantage of this design is capable to reduce power dissipation and increase speed of an ADC. The design is simulated in 0.18 μm CMOS Technology with Cadence environment. Proposed design exhibits good accuracy and a low power consumption about 102 μW with operating sampling frequency 125 MHz and 1.8 V supply. Simulation results are reported and compared with earlier work done and improvements are observed in this work.

CMOS低功耗模拟电路设计

探讨了低功耗设计在便携设备中的重要性,并结合互补金属氧化物半导体(Complementary Metal Oxide Semiconductor,CMOS)环形振荡器的设计从不同角度阐述低功耗设计的要点。首先,介绍了低功耗设计的概念、背景以及其在现代便携设备中的应用。其次,讨论了动态功耗和静态功耗对电路的影响,提出相应的解决方法和优化措施。再次,从工艺调整和设计方法2个角度,详细介绍低功耗设计的方法。最后,结合具体的CMOS环形振荡器设计,展示了低功耗设计的实际应用和优势,为便携设备的高效、可靠运行提供了理论基础和技术支持。

Reliability of High Speed Ultra Low Voltage Differential CMOS Logic

In this paper, we present a solution to the ultra low voltage inverter by adding a keeper transistor in order to make the semi-floating-gate more stable and to reduce the current dissipation. Moreover, we also present a differential ULV inverter and elaborate on the reliability and fault tolerance of the gate. The differential ULV gate compared to both a former ULV gate and standard CMOS are given. The results are obtained through Monte-Carlo simulations.

Low Power Design of High Speed CMOS Pulse Stream Neuron Circuit

A new pulse stream neuron circuit is presented, which can be obtained in the digital CMOS process and combines both the merits of digital circuits and analog ones. The output is expressed by the frequency of the pulses with transfer characteristic, which is correspondent with the ideal sigmoid curve perfectly. Moreover, the pulse\|active strategy is introduced into the design of this CMOS pulse stream neuron circuit for the first time in order to reduce the power dissipation, which is applicable to the low\|power design of mixed\|signal circuits,too. A simple technical process and compact architecture make this circuit work at a higher speed and with lower power dissipation and smaller area.

A Low-Power CMOS Analog Front-End IC with Adjustable On-Chip Filters for Biosensors

This paper presents a low-power CMOS analog front-end (AFE) IC designed with a selectable on-chip dual AC/DC- coupled paths for bio-sensor applications. The DC-coupled path can be selected to sense a biosignal with useful DC information, and the AC-coupled path can be selected for sensing the AC content of the biosignal by attenuating the unwanted DC component. The AFE IC includes a DC-coupled instrumentation amplifier (INA), two variable-gain 1st-order low pass filters (LPF) with tunable cut-off frequencies, a fixed gain 2nd-order Sallen-Key high-pass filter (HPF) with tunable cut-off frequencies, a buffer and an 8-bit differential successive approximation register (SAR) ADC. The entire AFE channel is designed and fabricated in a proprietary 0.35-μm CMOS technology. Excluding an external buffer needed to properly drive the ADC, the measured AFE IC consumes only 2.37 μA/channel with an input referred noise of ~40 μVrms in [1 Hz, 1 kHz], and successfully displays proper ECG (electrocardiogram) and electrogram (EGM) waveforms for QRS peaks detection. We expect that the low-power dual-path design of this AFE IC can enable it to periodically record both the AC and the DC signals for proper sensing and calibration for various bio-sensing applications.