Modeling random telegraph signal noise in CMOS image sensor under low light based on binomial distribution

The random telegraph signal noise in the pixel source follower MOSFET is the principle component of the noise in the CMOS image sensor under low light. In this paper, the physical and statistical model of the random telegraph signal noise in the pixel source follower based on the binomial distribution is set up. The number of electrons captured or released by the oxide traps in the unit time is described as the random variables which obey the binomial distribution. As a result,the output states and the corresponding probabilities of the first and the second samples of the correlated double sampling circuit are acquired. The standard deviation of the output states after the correlated double sampling circuit can be obtained accordingly. In the simulation section, one hundred thousand samples of the source follower MOSFET have been simulated,and the simulation results show that the proposed model has the similar statistical characteristics with the existing models under the effect of the channel length and the density of the oxide trap. Moreover, the noise histogram of the proposed model has been evaluated at different environmental temperatures.

Analysis of proton and γ-ray radiation effects on CMOS active pixel sensors

Radiation effects on complementary metal-oxide-semiconductor（CMOS） active pixel sensors（APS） induced by proton and γ-ray are presented. The samples are manufactured with the standards of 0.35 μm CMOS technology. Two samples have been irradiated un-biased by 23 MeV protons with fluences of 1.43 × 10^11 protons/cm^2 and 2.14 × 10^11 protons/cm-2,respectively, while another sample has been exposed un-biased to 65 krad（Si） ^60Co γ-ray. The influences of radiation on the dark current, fixed-pattern noise under illumination, quantum efficiency, and conversion gain of the samples are investigated. The dark current, which increases drastically, is obtained by the theory based on thermal generation and the trap induced upon the irradiation. Both γ-ray and proton irradiation increase the non-uniformity of the signal, but the nonuniformity induced by protons is even worse. The degradation mechanisms of CMOS APS image sensors are analyzed,especially for the interaction induced by proton displacement damage and total ion dose（TID） damage.

Performance enhancement of CMOS terahertz detector by drain current

In this paper, we study the effect of the drain current on terahertz detection for Si metal-oxide semiconductor fieldeffect transistors（MOSFETs） both theoretically and experimentally. The analytical model, which is based on the smallsignal equivalent circuit of MOSFETs, predicts the significant improvement of the voltage responsivity Rv with the bias current. The experiment on antennas integrated with MOSFETs agrees with the analytical model, but the Rv improvement is accompanied first by a decrease, then an increase of the low-noise equivalent power（NEP） with the applied current. We determine the tradeoff between the low-NEP and high-Rv for the current-biased detectors. As the best-case scenario, we obtained an improvement of about six times in Rv without the cost of a higher NEP. We conclude that the current supply scheme can provide high-quality signal amplification in practical CMOS terahertz detection.

A 0.18μm CMOS dual-band low power low noise amplifier for a global navigation satellite system

This paper presents a dual-band low noise amplifier for the receiver of a global navigation satellite system. The differences between single band and multi-band design methods are discussed. The relevant parameter analysis and the details of circuit design are presented. The test chip was implemented in a TSMC 0.18 μm 1P4M RF CMOS process. The LNA achieves a gain of 16.8 dB/18.9 dB on 1.27 GHz/1.575 GHz. The measured noise figure is around 1.5-1.7 dB on both bands. The LNA consumes less than 4.3 mA of current from a 1.8 V power supply. The measurement results show consistency with the design. And the LNA can fully satisfy the demands of the GNSS receiver.

A 2.4-GHz low power dual gain low noise amplifier for ZigBee

This paper presents a fully differential dual gain low noise amplifier（DGLNA） for low power 2.45-GHz ZigBee/IEEE 802.15.4 applications.The effect of input parasitics on the inductively degenerated cascode LNA is analyzed.Circuit design details within the guidelines of the analysis are presented.The chip was implemented in SMIC 0.18-μm 1P6M RF/mixed signal CMOS process.The DGLNA achieves a maximum gain of 8 dB and a minimum gain of 1 dB with good input return loss.In high gain mode, the measured noise figure（NF） is 2.3-3 dB in the whole 2.45-GHz ISM band.The measured 1-dB compression point, IIP3 and IIP2 is-9, 1 and 33 dBm, respectively.The DGLNA consumes 2 mA of current from a 1.8 V power supply.

A low-noise widely tunable Gm-C filter with frequency calibration

A fourth-order Gm-C Chebyshev low-pass filter is presented as channel selection filter for reconfigurable multi-mode wireless receivers. Low-noise technologies are proposed in optimizing the noise characteristics of both the Gm cells and the filter topology. A frequency tuning strategy is used by tuning both the transconductance of the Gm cells and the capacitance of the capacitor banks. To achieve accurate cut-off frequencies, an on-chip calibration circuit is presented to compensate for the frequency inaccuracy introduced by process variation. The filter is fabricated in a 0.13 m CMOS process. It exhibits a wide programmable bandwidth from 322.5 k Hz to20 MHz. Measured results show that the filter has low input referred noise of 5.9 n V/（Hz）^（1/2） and high out-of-band IIP3 of 16.2 d Bm. It consumes 4.2 and 9.5 m W from a 1 V power supply at its lowest and highest cut-off frequencies respectively.

A 0.8–4.2 GHz monolithic all-digital PLL based frequency synthesizer for wireless communications

A 0.8–4.2 GHz monolithic all-digital PLL based frequency synthesizer for wireless communications is successfully realized by the 130 nm CMOS process. A series of novel methods are proposed in this paper.Two band DCOs with high frequency resolution are utilized to cover the frequency band of interest, which is as wide as 2.5 to 5 GHz. An overflow counter is proposed to prevent the ＂pulse-swallowing＂ phenomenon so as to significantly reduce the locking time. A NTW-clamp digital module is also proposed to prevent the overflow of the loop control word. A modified programmable divider is presented to prevent the failure operation at the boundary.The measurement results show that the output frequency range of this frequency synthesizer is 0.8–4.2 GHz. The locking time achieves a reduction of 84% at 2.68 GHz. The best in-band and out-band phase noise performances have reached –100 d Bc/Hz, and –125 d Bc/Hz respectively. The lowest reference spur is –58 d Bc.