基于CNFET的三值内容寻址存储器单元设计

通过对三值静态随机存储器(Static Random Access Memory,SRAM)单元和数据比较电路结构以及碳纳米场效应晶体管(Carbon Nanotube Field Effect Transistor,CNFET)的研究,提出了基于CNFET的三值内容寻址存储器单元设计方案。首先利用CNFET阈值可调特性和开关信号理论设计三值缓冲器,采用反馈控制连接技术实现三值SRAM存储;然后结合三值SRAM单元和三值逻辑原理设计三值内容寻址存储器单元;最后实验验证,所设计的三值内容寻址存储器单元具有正确的逻辑功能,且与三态内容寻址存储器单元相比功耗延时积(Power-Delay Product,PDP)降低约83%。

基于CNFET的三值脉冲型移位寄存器设计

通过对碳纳米场效应晶体管(Carbon Nanotube Field Effect Transistor,CNFET)多阈值特性和多值逻辑原理的研究,结合移位寄存器设计方法,提出基于CNFET的具有左移右移并入并出功能的三值脉冲型移位寄存器设计方案.该方案首先利用开关信号理论和CNFET特性设计三值D触发器;然后设计三值T运算电路,并实现数据选择器逻辑功能;最后,在此基础上设计基于CNFET的三值脉冲型移位寄存器.经实验验证,所设计的电路输出稳定,具有正确的逻辑功能,且与CMOS低功耗移位寄存器相比,功耗延时积(Power-Delay Product)降低76.7%.

基于三值文字运算的碳纳米场效应晶体管SRAM设计

通过对文字运算电路和三值存储器原理的分析,结合碳纳米场效应晶体管(Carbon Nanotube Field Effect Transistor,CNFET)的特性,提出一种基于三值文字电路的碳纳米场效应晶体管SRAM设计方案。该方案首先利用三值文字运算真值表和开关信号理论设计文字运算电路;然后采用文字0、文字1和文字2非运算电路实现三值SRAM的功能,利用传输门控制反馈回路降低三值写操作的动态功耗;最后实验验证,所设计的电路逻辑功能正确且与传统交叉耦合SRAM相比写速度提高49.2%。

基于CNFET的三值脉冲式D触发器设计

通过对脉冲式时序电路的研究,利用多值开关信号理论,设计基于碳纳米场效应晶体管的单边沿和双边沿三值脉冲式D触发器.该方案利用CNFET高速低功耗特征,结合多值逻辑电路的开关运算,简化函数表达式,优化电路结构,减少晶体管数量,达到了降低功耗的目的.经过HSPICE仿真结果表明,所设计的三值脉冲式D触发器具有正确的逻辑功能和低功耗特性.

基于CNFET的三值逐次逼近ADC设计

模数转换器(Analog-to-Digital Converter,ADC)是片上集成系统的关键部件,通过对逐次逼近逻辑电路和三值逻辑原理的研究,提出了一种基于碳纳米场效应晶体管(Carbon Nanotube Field Effect Transistor,CNFET)的三值逐次逼近ADC设计方案。该方案首先控制三值电容阵列的底板电压,逐次逼近其模拟量值,产生由高位到低位的二值信号,然后由编码器将二值转换为三值信号,完成整个转换过程,最后实验证明了所设计的电路逻辑功能正确,并具有明显的高速、低功耗特性。

A low-voltage and energy-efficient full adder cell based on carbon nanotube technology

Scaling problems and limitations of conventional silicon transistors have led the designers to exploit novel nano-technologies. One of the most promising and feasible nano-technologies is CNT(Carbon Nanotube) based transistors. In this paper, a high-speed and energy-efficient CNFET(Carbon Nanotube Field Effect Transistor) based Full Adder cell is proposed for nanotechnology. This design is simulated in various supply voltages, frequencies and load capacitors using HSPICE circuit simulator. Significant improvement is achieved in terms of speed and PDP(Power-Delay-Product) in comparison with other classical and state-of-the-art CMOS and CNFET-based designs, existing in the literature. The proposed Full Adder can also drive large load capacitance and works properly in low supply voltages.

Comparative Performance Evaluation of Large FPGAs with CNFET-and CMOS-based Switches in Nanoscale

Routing resources are the major bottlenecks in improving the performance and power consumption of the current FPGAs. Recently reported researches have shown that carbon nanotube field effect transistors(CNFETs) have considerable potentials for improving the delay and power consumption of the modern FPGAs. In this paper, hybrid CNFET-CMOS architecture is presented for FPGAs and then this architecture is evaluated to be used in modern FPGAs. In addition, we have designed and parameterized the CNFET-based FPGA switches and calibrated them for being utilized in FPGAs at 45 nm, 22 nm and 16 nm technology nodes.Simulation results show that the CNFET-based FPGA switches improve the current FPGAs in terms of performance, power consumption and immunity to process and temperature variations. Simulation results and analyses also demonstrate that the performance of the FPGAs is improved about 30%, on average and the average and leakage power consumptions are reduced more than 6% and 98% respectively when the CNFET switches are used instead of MOSFET FPGA switches. Moreover, this technique leads to more than 20.31%smaller area. It is worth mentioning that the advantages of CNFET-based FPGAs are more considerable when the size of FPGAs grows and also when the technology node becomes smaller.

Impacts of Parameter Scaling for Low-Power Applications Using CNTFET （Carbon Nanotube Field Effect Transistor） Models： A Comparative Assessment

This paper provides an extension to the earlier work wherein a comparison between different models that had studied the effects of several parameters scaling on the performance of carbon nano tube field-effect transistors was presented. The evaluation for the studied models, with regard to the scaling effects, was to determine those which best reflect the very essence of carbon nano-tube technologies. Whereas the models subject this comparison （Fettoy, Roy, Stanford, and Southampton） were affected to varying degrees due to such parametric variations, the Stanford model was shown as still being valid for a wide range of chiralities and diameter sizes; a model that is also applicable for circuit simulations. In this paper, we present a comparative assessment of the various models subject to the study with regard to the effect of incorporating multiple carbon nanotubes in the channel region. We also assess the effect of oxide thickness on transistor performance in terms of the supply voltage threshold effects. Results leveraging our findings in this ongoing research endeavor reveal that many research efforts were not efficient to high degree due to high delay and not valid for circuit simulations.

A low standby-power fast carbon nanotube ternary SRAM cell with improved stability

Power dissipation, speed and stability are the most important parameters for multiple-valued SRAM design. To reduce the power consumption and further improve the performance of the ternary SRAM cell, we propose a low standby-power fast ternary SRAM cell based on carbon nanotube field effect transistors(CNFETs).The performance is simulated in terms of three criteria including standby-power, delay(write and read) and stability(RSNM). Compared to the novel ternary SRAM cell, our results show that the average standby-power, write and read delay of the proposed cell are reduced by 78.1%, 39.6% and 58.2%, respectively. In addition, the RSNM under process variations is 2.01× and 1.95× of the conventional and novel ternary SRAM cells, respectively.

MOSFET-like CNFET based logic gate library for low-power application:a comparative study

The next generation oflogic gate devices are expected to depend upon radically new technologies mainly due to the increasing difficulties and limitations of existing CMOS technology. MOSFET like CNFETs should ideally be the best devices to work with for high-performance VLS1. This paper presents results of a comprehensive comparative study of MOSFET-like carbon nanotube field effect transistors （CNFETs） technology based logic gate library for high-speed, low-power operation than conventional bulk CMOS libraries. It focuses on comparing four promising logic families namely： complementary-CMOS （C-CMOS）, transmission gate （TG）, complementary pass logic （CPL） and Domino logic （DL） styles are presented. Based on these logic styles, the proposed library of static and dynamic NAND-NOR logic gates, XOR, multiplexer and full adder functions are implemented efficiently and carefully analyzed with a test bench to measure propagation delay and power dissipation as a function of supply voltage. This analysis provides the right choice of logic style for low-power, high-speed applications. Proposed logic gates libraries are simulated using Synopsys HSPICE based on the standard 32 nm CNFET model. The simulation results demonstrate that, it is best to use C-CMOS logic style gates that are implemented in CNFET technology which are superior in performance compared to other logic styles, because of their low average powerdelay-product （PDP）. The analysis also demonstrates how the optimum supply voltage varies with logic styles in ultra-low power systems. The robustness of the proposed logic gate library is also compared with conventional and state-art of CMOS logic gate libraries.

Performance optimization of MOS-like carbon nanotube-FETs with realistic source/drain contacts based on electrostatic doping

Due to carrier band-to-band-tunneling （BTBT） through channel-source/drain contacts, conventional MOS- like Carbon Nanotube Field Effect Transistors （C-CNFETs） suffer from ambipolar conductance, which deteriorates the device performance greatly. In order to reduce such ambipolar behavior, a novel device structure based on electrostatic doping is proposed and all kinds of source/drain contacting conditions are considered in this paper. The non-equilibrium Green＇s function （NEGF） formalism based simulation results show that, with proper choice of tuning voltage, such electrostatic doping strategy can not only reduce the ambipolar conductance but also improve the sub-threshold perfor- mance, even with source/drain contacts being of Schottky type. And these are both quite desirable in circuit design to reduce the system power and improve the frequency as well. Further study reveals that the performance of the proposed design depends strongly on the choice of tuning voltage value, which should be paid much attention to obtain a proper trade-off between power and speed in application.

CNFET-based voltage rectifier circuit for biomedical implantable applications

Carbon nanotube field effect transistor（CNFET） shows lower threshold voltage and smaller leakage current in comparison to its CMOS counterpart. In this paper, two kinds of CNFET-based rectifiers, full-wave rectifiers and voltage doubler rectifiers are presented for biomedical implantable applications. Based on the standard 32 nm CNFET model, the electrical performance of CNFET rectifiers is analyzed and compared. Simulation results show the voltage conversion efficiency（VCE） and power conversion efficiency（PCE） achieve 70.82% and 72.49% for CNFET full-wave rectifiers and 56.60% and 61.17% for CNFET voltage double rectifiers at typical 1.0 V input voltage excitation, which are higher than that of CMOS design. Moreover, considering the controllable property of CNFET threshold voltage, the effect of various design parameters on the electrical performance is investigated.It is observed that the VCE and PCE of CNFET rectifier increase with increasing CNT diameter and number of tubes. The proposed results would provide some guidelines for design and optimization of CNFET-based rectifier circuits.