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On-line Cache Resizing for Low-Power Microprocessors
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作者 陈黎明 邹雪城 +1 位作者 雷鑑铭 刘政林 《Journal of Southwest Jiaotong University(English Edition)》 2009年第2期113-122,共10页
We propose a novel scheme, called on-line cache resizing (OCR), to dynamically resize the cache and meet the size requirement of each application. At each periodic interval, the scheme gathers the cache hit-miss sta... We propose a novel scheme, called on-line cache resizing (OCR), to dynamically resize the cache and meet the size requirement of each application. At each periodic interval, the scheme gathers the cache hit-miss statistics at runtime using an extra tag array. These executing statistics serve as inputs to an analytical model of cache energy. The scheme uses energy as a primary metric to dynamically increase/decrease the number of active cache ways for the next interval. The scheme minimizes the active cache size to save energy with minimal performance loss. The simulation with SPEC 2000 benchmarks shows that OCR results in an average of 38.4% energy saving compared with fixed-size caches, with only 2.0% performance loss. 展开更多
关键词 Low power cache cache resizing MICROPROCESSOR
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