Unique Characteristics of Vertical Carbon Nanotube Field-effect Transistors on Silicon

A vertical carbon nanotube field-effect transistor(CNTFET) based on silicon(Si) substrate has been proposed and simulated using a semi-classical theory. A single-walled carbon nanotube(SWNT) and an n-type Si nanowire in series construct the channel of the transistor. The CNTFET presents ambipolar characteristics at positive drain voltage(Vd) and n-type characteristics at negative Vd. The current is significantly influenced by the doping level of n-Si and the SWNT band gap. The n-branch current of the ambipolar characteristics increases with increasing doping level of the n-Si while the p-branch current decreases. The SWNT band gap has the same influence on the p-branch current at a positive Vd and n-type characteristics at negative Vd. The lower the SWNT band gap, the higher the current. However, it has no impact on the n-branch current in the ambipolar characteristics. Thick oxide is found to significantly degrade the current and the subthreshold slope of the CNTFETs.

A voltage-controlled chaotic oscillator based on carbon nanotube field-effect transistor for low-power embedded systems

This paper presents a compact and low-power-based discrete-time chaotic oscillator based on a carbon nanotube field-effect transistor implemented using Wong and Deng＇s well-known model. The chaotic circuit is composed of a nonlinear circuit that creates an adjustable chaos map, two sample and hold cells for capture and delay functions, and a voltage shifter that works as a buffer and adjusts the output voltage for feedback. The operation of the chaotic circuit is verified with the SPICE software package, which uses a supply voltage of 0.9 V at a frequency of 20 kHz. The time series, frequency spectra, transitions in phase space, sensitivity with the initial condition diagrams, and bifurcation phenomena are presented. The main advantage of this circuit is that its chaotic signal can be generated while dissipating approximately 7.8 μW of power, making it suitable for embedded systems where many chaos-signal generators are required on a single chip.

Designing a Carbon Nanotube Field-Effect Transistor with High Transition Frequency for Ultra-Wideband Application

Theoretical calculations predict transition frequencies in the terahertz range for the field-effect transistors based on carbon nanotubes, and this shows their suitability for being used in high frequency applications. In this paper, we have designed a field-effect transistor based on carbon nanotube with high transition frequency suitable for ultra-wide band applications. We did this by optimizing nanotube diameter, gate insulator thickness and dielectric constant. As a result, we achieved the transition frequency about 7.45 THz. The environment of open source software FETToy is used to simulate the device. Also a suitable model for calculating the transition frequency is presented.

Impacts of Parameter Scaling for Low-Power Applications Using CNTFET （Carbon Nanotube Field Effect Transistor） Models： A Comparative Assessment

This paper provides an extension to the earlier work wherein a comparison between different models that had studied the effects of several parameters scaling on the performance of carbon nano tube field-effect transistors was presented. The evaluation for the studied models, with regard to the scaling effects, was to determine those which best reflect the very essence of carbon nano-tube technologies. Whereas the models subject this comparison （Fettoy, Roy, Stanford, and Southampton） were affected to varying degrees due to such parametric variations, the Stanford model was shown as still being valid for a wide range of chiralities and diameter sizes; a model that is also applicable for circuit simulations. In this paper, we present a comparative assessment of the various models subject to the study with regard to the effect of incorporating multiple carbon nanotubes in the channel region. We also assess the effect of oxide thickness on transistor performance in terms of the supply voltage threshold effects. Results leveraging our findings in this ongoing research endeavor reveal that many research efforts were not efficient to high degree due to high delay and not valid for circuit simulations.

Carbon nanotube integrated circuit technology:purification,assembly and integration

As the manufacturing process of silicon-based integrated circuits(ICs)approaches its physical limit,the quantum effect of silicon-based field-effect transistors(FETs)has become increasingly evident.And the burgeoning carbon-based semiconductor technology has become one of the most disruptive technologies in the post-Moore era.As one-dimensional nanomaterials,carbon nanotubes(CNTs)are far superior to silicon at the same technology nodes of FETs because of their excellent electrical transport and scaling properties,rendering them the most competitive material in the next-generation ICs technology.However,certain challenges impede the industrialization of CNTs,particularly in terms of material preparation,which significantly hinders the development of CNT-based ICs.Focusing on CNT-based ICs technology,this review summarizes its main technical status,development trends,existing challenges,and future development directions.

Design of Multi-Valued Logic Circuit Using Carbon Nano Tube Field Transistors

The design of a three-input logic circuit using carbon nanotube field effect transistors(CNTFETs)is presented.Ternary logic must be an exact replacement for dual logic since it performs straightforwardly in digital devices,which is why this design is so popular,and it also reduces chip area,both of which are examples of circuit overheads.The proposed module we have investigated is a triple-logic-based one,based on advanced technology CNTFETs and an emphasis on minimizing delay times at various values,as well as comparisons of the design working with various load capacitances.Comparing the proposed design with the existing design,the delay times was reduced from 66.32 to 16.41 ps,i.e.,a 75.26%reduction.However,the power dissipation was not optimized,and increased by 1.44%compared to the existing adder.The number of transistors was also reduced,and the product of power and delay(P∗D)achieved a value of 0.0498053 fJ.An improvement at 1 V was also achieved.A load capacitance(fF)was measured at different values,and the average delay measured for different values of capacitance had a maximum of 83.60 ps and a minimum of 22.54 ps,with a range of 61.06 ps.The power dissipations ranged from a minimum of 3.38μW to a maximum of 6.49μW.Based on these results,the use of this CNTFET half-adder design in multiple Boolean circuits will be a useful addition to circuit design.

Field-effect transistors with multiple channels constructed by carbon nanotubes

Single-wall carbon nanotubes (SWNTs) pre-decorated with functional molecules are directly aligned in the AC electric field, which makes SWNTs parallelly bridge the source and drain electrodes and act as the multiple conduction channels of the field-effect transistor (FET). The method avoids the mutual tanglement of SWNTs and makes them align between the source and drain electrodes abreast and dispersedly. It is indicated that aligning SWNTs in the high-volatility solvents can decrease the contaminant around the electrodes and has a function to purify the raw SWNTs. The obtained multi-channel FET not only takes on a high transconductance, but also holds the good reliability and stability.

High yield fabrication of semiconducting thin-film field-effect transistors based on chemically functionalized single-walled carbon nanotubes

Here we report a simple and scalable method to fabricate high performance thin-film field-effect transistors(FETs) with high yield based on chemically functionalized single-walled carbon nanotubes(SWNTs) by organic radical initiators.The UV-Vis-NIR spectra,Raman spectra and electrical characterization demonstrated that metallic species in CoMoCat 65 and HiPco SWNTs could be effectively eliminated after reaction with some organic radical initiators.The effects of the substrate properties on the electrical properties of FET devices were investigated,and the results showed that the electrical properties of FET devices fabricated on high hydrophobic substrates were better than those on low hydrophobic substrates.Furthermore,it was found that FET devices based on 1,1'-azobis(cyanocyclohexane)(ACN)-modified CoMoCat 65 SWNTs exhibited more excellent electrical performance with effective mobility of ～11.8 cm2/Vs and on/off ratio of ～2×105 as compared with benzoyl peroxide(BPO)-modified CoMoCat 65 SWNTs and lauoryl peroxideand(LPO)-modified HiPco SWNTs,likely due to the introduction of the electron-withdrawing groups(CN group) on the SWNT surface.This method does not require nontrivial reaction conditions or complicated purification after reaction,therefore promising low-cost production of high-performance devices for macroelectronics.

Suppression of leakage current in carbon nanotube field-effect transistors

Carbon nanotube field-effect transistor(CNT FET)has been considered as a promising candidate for future high-performance and low-power integrated circuits(ICs)applications owing to its ballistic transport and excellent immunity to short channel effects(SCEs).Still,it easily suffers from the ambipolar property,and severe leakage current at off-state originated from gate-induced drain leakage(GIDL)in CNT FETs with small bandgap.Although some modifications on device structure have been experimentally demonstrated to suppress the leakage current in CNT FETs,there is still a lack of the structure with excellent scalability,which will hamper the development of CNT FETs toward a competitive technology node.Here,we explore how the device geometry design affects the leakage current in CNT FETs,and then propose the possible device structures to suppress off-state current and check their availability through the two-dimensional(2D)TCAD simulations.Among all the proposed structures,the L-shaped-spacer CNT FET exhibits significantly suppressed leakage current and excellent scalability down to sub-50 nm with a simple self-aligned gate process.According to the simulation results,the 50 nm gate-length L-shaped-spacer CNT FET exhibits an off-state current as low as approximately 1 nA/μm and an on-current as high as about 2.1 mA/μm at a supply voltage of-1 V and then can be extended as a universal device structure to suppress leakage current for all the narrow-bandgap semiconductors based FETs.

Drain-engineered carbon-nanotube-film field-effect transistors with high performance and ultra-low current leakage

A small bandgap and light carrier effective mass(mo)lead to obv ous ambipolar transport behavior in carbon nanotube(CNT)fild-effect transistors(FE Ts),including a high off-state current and severe degradation of the subthreshold swing(SS)with increasing drain bias voltage.We demonstrate a drain-engineered method to cope with this common problem in CNT-film FETs with a sub-μum channel length,i.e.,suppressing the ambipolar behavion while maintaining high on-state performance by adopting a feedback gate(FBG)structure to extend the drain region from the CNT/metal contact to the proximate CNT channels to suppress the tunneling current.Sub-400-nm-channel-length FETs with a FBG structure statistially present a high on/off ratio of up to 10*and a sub-200 mV/dec SS under a high drain bias of up to-2 V whle maintaining a high on-state current of 0.2 mA/μm or a peak transconductance of 0.2 mS/um.By lowering the supply voltage to 1.5 V,FBG CNT-fim FETs can meet the requirement of standard-pertormance ultra large scale integrated circuits(ULSICs).Therefore,the introduction of the drain engineering structure enables applications of CNT-film-based FETs in ULSICs and could also be widely extended to other small-bandgap semiconductor-based FETs for an improvement in their off-state property.

Coaxial boron nitride nanotubes as interfacial dielectric layers to lower interface trap density in carbon nanotube transistors

A semiconductor/dielectric interface is one of the dominant factors in device characteristics,and a variety of oxides with high dielectric constants and low interface trap densities have been used in carbon nanotube transistors.Given the crystal structure of nanotubes with no dangling bonds,there remains room to investigate unconventional dielectric materials.Here,we fabricate carbon nanotube transistors with boron nitride nanotubes as interfacial layers between channels and gate dielectrics,where a single semiconducting nanotube is used to focus on switching behaviors at the subthreshold regime.The subthreshold swing of 68 mV·dec^(−1)is obtained despite a 100-nm-thick Sio_(2)dielectric,corresponding to the effective interface trap density of 5.2×10^(11)cm^(−2)·eV^(−1),one order of magnitude lower than those of carbon nanotube devices without boron nitride passivation.The interfacial layers also result in the mild suppression of threshold voltage variation and hysteresis.We achieve Ohmic contacts through the selective etching of boron nitride nanotubes with XeF2 gas,overcoming the trade-off imposed by wrapping the inner nanotubes.Negligible impacts of fluorinating carbon nanotubes on device performances are also confirmed as long as the etching is applied exclusively at source/drain regions.Our results represent an important step toward nanoelectronics that exploit the advantage of one-dimensional van der Waals heterostructures.

Reliability tests and improvements for Sc-contacted n-type carbon nanotube transistors

Scandium （Sc） contacted n-type carbon nanotube （CNT） field-effected transistors （FETs） with back and top-gate structure have been fabricated, and their stability in air were investigated. It was shown that oxygen and water molecules may affect both the nanotube channel and Scinanotube contacts, leading to deteriorated contact quality and device performance. These negative effects associated with the instability of n-type carbon nanotube FETs can be eliminated through passivating the CNT devices by a thin layer of atomic-layer-deposition grown A1203 insulator. After passivation, the n-type carbon nanotube FETs are shown to exhibit excellent atmosphere stability even after being tested and exposed to air for over 146 days, and then much smoother output characteristics and reduced gate voltage hysteresis from I to 0.1 V were demonstrated when compared with devices without passivation. Lasting power-on tests were also performed on the passivated CNT FETs under large gate stress and high drain current in air for at least 10 h, revealing null device degradation and sometimes even improved performance. These results promise that passivated CNT devices are reliable in air and may be used in practical applications.

Monolithic three-dimensional integration of aligned carbon nanotube transistors for high-performance integrated circuits

Carbon nanotube field-effect transistors(CNT FETs)have been demonstrated to exhibit high performance only through low-temperature fabrication process and require a low thermal budget to construct monolithic three-dimensional(M3D)integrated circuits(ICs),which have been considered a promising tech-nology to meet the demands of high-bandwidth computing and fully func-tional integration.However,the lack of high-quality CNT materials at the upper layer and a low-parasitic interlayer dielectric(ILD)makes the reported M3D CNT FETs and ICs unable to provide the predicted high performance.In this work,we demonstrate a multilayer stackable process for M3D integration of high-performance aligned carbon nanotube(A-CNT)transistors and ICs.A low-κ(-3)interlayer SiO_(2)layer is prepared from spin-on-glass(SOG)through processes with a highest temperature of 220℃,presenting low parasitic capaci-tance between two transistor layers and excellent planarization to offer an ideal surface for the A-CNT and device fabrication process.A high-quality A-CNT film with a carrier mobility of 650 cm 2 V^(-1)s^(-1)is prepared on the ILD layer through a clean transfer process,enabling the upper CNT FETs fabri-cated with a low-temperature process to exhibit high on-state current(1 mAμm^(-1))and peak transconductance(0.98 mSμm^(-1)).The bottom A-CNT FETs maintain pristine high performance after undergoing the ILD growth and upper FET fabrication.As a result,5-stage ring oscillators utilizing the M3D architecture show a gate propagation delay of 17 ps and an active region of approximately 100μm 2,representing the fastest and the most compact M3D ICs to date.

Wafer-scale fabrication of carbon-nanotube-based CMOS transistors and circuits with high thermal stability

Thanks to its single-atomic-layer structure,high carrier transport,and low power dissipation,carbon nanotube electronics is a leading candidate towards beyond-silicon technologies.Its low temperature fabrication processes enable three-dimensional(3D)integration with logic and memory(static random access memory(SRAM),magnetic random access memory(MRAM),resistive random access memory(RRAM),etc.)to realize efficient near-memory computing.Importantly,carbon nanotube transistors require good thermal stability up to 400℃ processing temperature to be compatible with back-end-of-line(BEOL)process,which has not been previously addressed.In this work,we developed a robust wafer-scale process to build complementary carbon nanotube transistors with high thermal stability and good uniformity,where AlN was employed as electrostatic doping layer.The gate stack and passivation layer were optimized to realize high-quality interfaces.Specifically,we demonstrate 1-bit carbon nanotube full adders working under 250℃ with rail-to-rail outputs.

Contactless probing of the intrinsic carrier transport single-walled carbon nanotubes

Intrinsic carrier transport properties of single-walled carbon nanotubes have been probed by two parallel methods on the same individual tubes： The contactless dielectric force microscopy （DFM） technique and the conventional field-effect transistor （FET） method. The dielectric responses of SWNTs are strongly correlated with electronic transport of the corresponding FETs. The DC bias voltage in DFM plays a role analogous to the gate voltage in FET. A microscopic model based on the general continuity equation and numerical simulation is built to reveal the link between intrinsic properties such as carrier concentration and mobility and the macroscopic observable, i.e. dielectric responses, in DFM experiments. Local transport barriers in nanotubes, which influence the device transport behaviors, are also detected with nanometer scale resolution.

基于碳基500nm工艺的双采样真随机数发生器

碳纳米管场效应晶体管(CNTFET)因其极小的尺寸、超高的载流子迁移率、准一维结构的弹道输运等特性,顺应了未来集成电路高集成化和微型化的发展趋势。基于课题组构建的500 nm碳基工艺设计包,设计了一款真随机数发生器(TRNG)。碳基真随机数发生器利用慢时钟振荡器对快时钟振荡器进行采样获取随机源,通过在慢时钟振荡器中添加电阻热噪声以增加环形振荡器的相位抖动,经单比特频数测试、重叠子序列检测等随机性测试,证实本设计提高了熵源的非相关性与不可预测性。碳基真随机数发生器的最高工作频率达到7.04 MHz,功耗为1.98 mW,版图面积为2.3 mm×1.5 mm。输出序列通过了随机性检验,适用于现代密码系统的纳米级芯片。

Investigation of charge interaction between fullerene derivatives and single-walled carbon nanotubes

The charge interaction and corresponding doping effect between single-walled carbonnanotubes (SWNTs) and various fullerene derivatives, namely, C60, phenyl-C61-butyricacid methyl ester (PC61BM), methano-indenefullerene (MIF), 10,100,40,400-tetrahydrodi[1,4]methanonaphthaleno[5,6]fullerene (ICBA), 1,4-bis(dimethylphenylsilylmethyl)[60]fullerene (SIMEF-1), and dimethyl(orthoanisyl) silylmethyl(dimethylphenylsilylmethyl)[60]fullerene (SIMEF-2), are investigated. A variety of analytical techniques,including field-effect transistors (FETs) made of horizontally aligned arrays ofSWNTs, is used as a means of investigation. Data from different measurements haveto be used to obtain a concrete evaluation for the fullerene-applied SWNTs. The datacollectively points toward the conclusion that fullerenes with high molecular orbitalenergy levels, namely, MIF, SIMEF-1, SIMEF-2, and PC61BM, induce p-type doping,while fullerenes with low molecular orbital energy levels, namely, ICBA and C60,induce n-type doping on the carbon nanotubes. Nevertheless, the SWNTs retained ptypecharacteristics because n-doping induced by the fullerenes are weak compared tothe p-doping of the water and oxygen on carbon nanotubes. This means that fullerenederivatives have the ability to fine-tune the energy levels of carbon nanotubes, whichcan play a crucial role in carbon nanotube-based electronics, such as solar cells, lightemittingdevices, and FETs.

Carbon nanomaterials： controlled growth and field-effect transistor biosensors

Carbon nanostructures, including carbon nanotubes （CNTs） and gra- phene, have been studied extensively due to their special structures, excellent electrical properties and high chemical stability. With the development of nanotechnology and nanoscience, various methods have been developed to synthesize CNTs/graphene and to assemble them into microelectroniclsensor devices. In this review, we mainly demon- strate the latest progress in synthesis of CNTs and graphene and their applications in field-effect transistors （FETs） for biological sensors.

碳纳米管/金属接触改善方法的研究进展

碳纳米管(CNT)由于其独特结构和优异特性已被广泛用来构筑各种纳米器件.而CNT与电极间的接触在CNT器件中扮演着重要的作用,是器件性能的关键影响因素.采用何种有效的方法来改善CNT与金属电极间的接触一直是CNT器件研究中的一个重要方面.本文综述了近年来CNT/金属接触改善方法的研究进展,结合本课题组的研究对目前有代表性的接触改善方法进行介绍.阐述了各种改善方法的原理和加工工艺,讨论了采用这些方法获得的接触特性和器件性能,并对各方法的特点进行了比较.

碳纳米管的快速糖基化及用于糖-凝集素特异性识别作用的研究

将含糖基的简单两亲分子N-十八烷基麦芽糖酰胺(N-n-Octadecyl-D-maltonamide,NOMA)非共价修饰到单壁碳纳米管(SWNT)表面形成糖-碳纳米管复合体(NOMA-SWNT),谱学和形态学结果表明,NOMA不仅能快速、高效地吸附到SWNT表面,而且能有效地改善SWNT在水溶液中的分散性能.以NOMA-SWNT管束为导通沟道构建了碳纳米管场效应管(CNTFET)器件,检测了麦芽糖和伴刀豆凝集素蛋白(Con A)的特异性识别作用.检测器件在每个修饰阶段的电学性能的变化证明了NOMA对SWNT的非共价糖基化修饰及用CNTFET来检测糖-凝集素特异性识别作用的可能性.