An NMOS output-capacitorless low-dropout regulator with dynamic-strength event-driven charge pump

In this paper,an NMOS output-capacitorless low-dropout regulator(OCL-LDO)featuring dual-loop regulation has been proposed,achieving fast transient response with low power consumption.An event-driven charge pump(CP)loop with the dynamic strength control(DSC),is proposed in this paper,which overcomes trade-offs inherent in conventional structures.The presented design addresses and resolves the large signal stability issue,which has been previously overlooked in the event-driven charge pump structure.This breakthrough allows for the full exploitation of the charge-pump structure's poten-tial,particularly in enhancing transient recovery.Moreover,a dynamic error amplifier is utilized to attain precise regulation of the steady-state output voltage,leading to favorable static characteristics.A prototype chip has been fabricated in 65 nm CMOS technology.The measurement results show that the proposed OCL-LDO achieves a 410 nA low quiescent current(IQ)and can recover within 30 ns under 200 mA/10 ns loading change.

Ultra-Robust and High-Performance Rotational Triboelectric Nanogenerator by Bearing Charge Pumping

As an emerging technology to convert environmental high-entropy energy into electrical energy,triboelectric nanogenerator(TENG)has great demands for further enhancing the service lifetime and output performance in practical applications.Here,an ultra-robust and high-performance rotational triboelectric nanogenerator(R-TENG)by bearing charge pumping is proposed.The R-TENG composes of a pumping TENG(P-TENG),an output TENG(O-TENG),a voltage-multiplying circuit(VMC),and a buffer capacitor.The P-TENG is designed with freestanding mode based on a rolling ball bearing,which can also act as the rotating mechanical energy harvester.The output low charge from the P-TENG is accumulated and pumped to the non-contact O-TENG,which can simultaneously realize ultralow mechanical wear and high output performance.The matched instantaneous power of R-TENG is increased by 32 times under 300 r/min.Furthermore,the transferring charge of R-TENG can remain 95%during 15 days(6.4×10^(6)cycles)continuous operation.This work presents a realizable method to further enhance the durability of TENG,which would facilitate the practical applications of high-performance TENG in harvesting distributed ambient micro mechanical energy.

Research and Design of an On-Chip High Efficiency Dual-Output Charge Pump

To meet the demands for different supply voltage levels on SOC required by digital modules like CPU core and analog modules,a novel dual-output charge pump is proposed. The charge pump can output a step-up and a step-down voltage simultaneously with a high driving capability. The multiple gain pair technique was introduced to enhance its efficiency. The proposed co-use technology for capacitors and switch arrays reduced its cost. The charge pump was designed and fabricated in a TSMC 0.35μm mixed-signal CMOS process. A group of analytical equations were derived to model its static characteristics. A state-space model was derived to describe its small-signal dynamic behavior. Analytical predictions were verified by Spectre simulation and testing. The consistency of simulated results as well as test results with analytical predictions demonstrated the high precision of the derived analytical equations and the developed models.

An Improved Charge-Averaging Charge Pump for a Fractional-N Frequency Synthesizer

An improved charge-averaging charge pump and the corresponding circuit implementation are presented. The charge-averaging charge pump proposed by Koo is analyzed and a new scheme is proposed. This new scheme decreases power by 1/3 and eliminates the practical defects in the original. Spectre Verilog behavioral simulation results show that the proposed scheme can strongly reduce the energy of spurs. Circuit implementation of this new charge pump for a frequency synthesizer with a fractional division ratio of 1/3 is then presented and multi-level simulation is performed to validate its feasibility at the circuit level. The simulation results show this new scheme outputs a flat voltage curve in a locked state and can thus effectively suppress fraction spurs.

A Novel All-pMOS AC to DC Charge Pump with High Efficiency

A novel AC to DC charge pump with high performance is presented. Due to the pMOS structure and threshold voltage canceling technology, the efficiency and the output voltage are greatly improved. Test results show that the output voltage and power efficiency are improved by 125% and 104% respectively at 13.56MHz for a 1V sinusoidal input compared to the traditional MOS diodes structure.

An Improved Charge Pumping Method to Study Distribution of Trapped Charges in SONOS Memory

In silicon-oxide-nitride-oxide-silicon （SONOS） memory and other charge trapping memories, the charge distribution after programming operation has great impact on the devic＇s characteristics,such as reading,programming/erasing, and reliability. The lateral distribution of injected charges can be measured precisely using the charge pumping method. To improve the precision of the actual measurement, a combination of a constant low voltage method and a constant high voltage method is introduced during the charge pumping testing of the drain side and the source side, respectively. Finally, the electron distribution after channel hot electron programming in SONOS memory is obtained,which is close to the drain side with a width of about 50nm.

Design of a CMOS Adaptive Charge Pump with Dynamic Current Matching

A novel structure for a charge pump circuit is proposed, in which the charge-pump （CP） current can adaptively regulated according to phase-locked loops （PLL） frequency synthesis demand. The current follow technology is used to make perfect current matching characteristics, and the two differential inverters are implanted to increase the speed of charge pump and decrease output spur due to theory of low voltage difference signal. Simulation results, with 1st silicon 0. 25μm 2. 5 V complementary metal-oxide-semiconductor （CMOS） mixed-signal process, show the good current matching characteristics regardless of the charge pump output voltages.

Valley-polarized pumping current in zigzag graphene nanoribbons with different spatial symmetries

We numerically investigate the valley-polarized current in symmetric and asymmetric zigzag graphene nanoribbons(ZGNRs) by the adiabatic pump, and the effect of spatial symmetry is considered by introducing different pumping regions. It is found that pumping potentials with the symmetry Vp(x,y) = Vp(-x,y)can generate the largest valleypolarized current. The valley-polarized currents I13~L with the pumping potential symmetry Vp(x,y) =Vp(x,-y,) and I14~L with Vp(x,y) = Vp(-x,-y) of symmetric ZGNRs are much smaller than those of asymmetric ZGNRs. We also find I13~L and I14~L of symmetric ZGNRs decrease and increase with the increasing pumping amplitude, respectively. Moreover, the dephasing effect from the electron-phonon coupling within the Buttiker dephasing scheme is introduced. The valley-polarized current of the symmetric ZGNRs with Vp(x,y)= Vp(x,-y) increases with the increase of the dephasing strength while that with Vp(x,y) = Vp(-x,-y) decreases as the dephasing strength increases.

Self-Balanced Charge Pump with Fast Lock Circuit

A self-balanced charge pump （CP） with fast lock circuit to achieve nearly zero phase error is proposed and analyzed. The proposed CP is designed based on the SMIC 0.25μm 1P5M complementary metal oxide semiconductor （CMOS） process with a 2.5 V supply voltage, HSPICE simulation shows that even if the mismatch of phase/frequency detector （PFD） was beyond 10%, the charge pump could still keep nearly zero phase error, Incorporated fast lock circuit can shorten start-up time to below 300 ns.

Spin-current pump in silicene

We report a theoretical study of pumped spin currents in a silicene-based pump device,where two time-dependent staggered potentials are introduced through the perpendicular electric fields and a magnetic insulator is considered in between the two pumping potentials to magnetize the Dirac electrons.It is shown that giant spin currents can be generated in the pump device because the pumping can be optimal for each transport mode,the pumping current is quantized.By controlling the relevant parameters of the device,both pure spin currents and fully spin-polarized currents can be obtained.Our results may shed a new light on the generation of pumped spin currents in Dirac-electron systems.

A PLL Clock Frequency Multiplier Using Dynamic Current Matching Adaptive Charge-Pump and VCO Frequency Reuse

A 3.5 times PLL clock frequency multiplier for low voltage different signal （LVDS） driver is presented. A novel adaptive charge pump can automatically switch the loop bandwidth and a voltage-controlled oscillator （VCO） is designed with the aid of frequency ranges reuse technology. The circuit is implemented using 1st Silicon 0.25 μm mixed-signal complementary metal-oxide-semiconductor （CMOS） process. Simulation results show that the PLL clock frequency multiplier has very low phase noise and very short capture time .

2.5Gb/s Monolithic IC of Clock Recovery,Data Decision,and 1∶4 Demultiplexer

A high integrated monolithic IC, with functions of clock recovery, data decision, and 1 ： 4 demultiplexer,is implemented in 0.25μm CMOS process for 2.5Gb/s fiber-optic communications. The recovered and frequency divided 625MHz clock has a phase noise of -106.26dBc/Hz at 100kHz offset in response to a 2.5Gb/s PRBS input data （2^31-1）. The 2.5Gb/s PRBS data are demultiplexed to four 625Mb/s data. The 0.97mm× 0.97mm IC consumes 550mW under a single 3.3V power supply （not including output buffers）.

A Low Jitter PLL in a 90nm CMOS Digital Process

A low jitter phase-locked loop （PLL） that does not need analog resistors and capacitors is designed and fabrica- ted in a 90nm CMOS digital process. The metal parasitic capacitor is used in the PLL loop filter. Test results show that when the PLL is locked on 1. 989GHz, the RMS jitter is 3. 7977ps, the peak-to-peak jitter is 31. 225ps, and the power con- sumption is about 9mW. The locked output frequency range is from 125MHz to 2.7GHz.

An Ultra-Low-Power Embedded EEPROM for Passive RFID Tags

An ultra-low-power,256-bit EEPROM is designed and implemented in a Chartered 0.35μm EEPROM process. The read state power consumption is optimized using a new sense amplifier structure and an optimized control circuit. Block programming/erasing is achieved using an improved control circuit. An on silicon program/erase/read access time measurement design is given. For a power supply voltage of 1.8V,an average power consumption of 68 and 0.6μA for the program/erase and read operations,respectively,can be achieved at 640kHz.

Analysis and Design of a Low-Cost RFID Tag Analog Front-End

A new,low-cost RFID tag analog front-end compatible with ISO 14443A and ISO 14443B is presented. By substituting conventional multi-circle antenna with single-circle antenna, the package cost of the tag is greatly reduced. Based on this exasperate antenna performance,a new rectifier with high power conversion efficiency and low turn-on voltage is presented. The circuit is implemented in an SMIC 0.18μm EEPROM process. Measurement results show that with a 120kΩ load,the power conversion efficiency reaches as high as 36%. For a sinusoidal wave with magnitude of 0. 5V, the output DC voltage reaches IV,which is high enough for RFID tags. The read distance is as far as 22cm.

A Low-Voltage,High Efficiency Power Generation Structure for UHF RFID

This paper presents a new power generation structure that can provide DC energy for passive UHF RFID with high sensitivity and high efficiency. The structure is designed with 0.18μm standard CMOS technology, including two charge pumps,a current reference, and a group of bias circuits. Low-voltage performance is improved thanks to the bias structure,which eliminates the threshold voltage drop and body-effect of conventional circuits. A 350mV minimum input level is required to generate a 1.5V power supply for a 100k~ load with power conversion efficiency （PCE） of 22%. PCE up to 29.8% is achieved with a 60kΩ load. Simulation results show that the new circuit is superior to conventional charge pumps.

A Novel Method to Compensate the Sigma-Delta Shaped Noise for Wide Band Fractional-N Frequency Synthesizers

A novel method to partially compensate sigma-delta shaped noise is proposed. By injecting the compensation current into the passive loop filter during the delay time of the phase frequency detector（PFD）,a maximum reduction of the phase noise by about 16dB can be achieved. Compared to other compensation methods,the technique proposed here is relatively simple and easy to implement. Key building blocks for realizing the noise cancellation,including the delay variable PFD and compensation current source, are specially designed. Both the behavior level and circuit level simulation results are presented.

Effect of Band Trap Band Current on DCIV Spectrum Peaks at LDD Drain Region in 0.275μm nMOST's

Interface traps generated under hot carrier (HC) stress in LDD nMOST's are monitored by the direct current current voltage (DCIV) measurement technique and charge pumping (CP) technique.The measured and analyzed results show that the D peak in DCIV spectrum,which related to the drain region,is affected by a superfluous drain leakage current.The band trap band tunneling current is dominant of this current.

A Novel Power Supply Solution of a Passive RFID Transponder

This paper presents a power supply solution for fully integrated passive radio-frequency identification （RFID） transponder IC, which has been implemented in 0.35μm CMOS technology with embedded EEPROM from Chartered Semiconductor. The proposed AC/DC and DC/DC charge pumps can generate stable output for RFID applications with quite low power dissipation and extremely high pumping efficiency. An analytical model of the voltage multiplier, comparison with other charge pumps, simulation results, and chip testing results are presented.

Power management unit chip design for automobile active-matrix organic light-emitting diode display module

A power management unit （PMU） chip supplying dual panel supply voltage, which has a low electro-magnetic interference （EMI） characteristic and is favorable for miniaturization, is designed. A two-phase charge pump circuit using external pumping capacitor increases its pumping current and works out the charge-loss problem by using bulk-potential biasing circuit. A low-power start-up circuit is also proposed to reduce the power consumption of the band-gap reference voltage generator. And the ring oscillator used in the ELVSS power circuit is designed with logic devices by supplying the logic power supply to reduce the layout area. The PMU chip is designed with MagnaChip＇s 0.25 μ high-voltage process. The driving currents of ELVDD and ELVSS are more than 50 mA when a SPICE simulation is done.