A stable LDO using VCCS （voltage control current source） is presented. The LDO is designed and implemented on GF 2P4M 0.35μm CMOS technology. Compared with a previous compensation scheme, VCCS can implement a real ...A stable LDO using VCCS （voltage control current source） is presented. The LDO is designed and implemented on GF 2P4M 0.35μm CMOS technology. Compared with a previous compensation scheme, VCCS can implement a real stable LDO with a small on-chip capacitor of 1 pF, whose stability is not affected by the variable ESR （equivalent series resistance） of the output capacitor. The unit gain frequency of the LDO loop can achieve 1.5 MHz, improving the transient response. The PSR of the LDO is larger than 45 dB within 0-40 kHz. The static current of the LDO at heavy load of 100 mA is 57 μA and the dropout voltage of the LDO is 150 mV. Experimental results show that a setting time of 10 ks is achieved, and the variation of output voltage is smaller than 35 mV for a 100 mA load step in transient response of the LDO.展开更多
基于Nuvoton 0.5μm 5 V标准CMOS工艺,设计了一种高稳定性、高瞬态响应、无片外电容低压差线性稳压器(LDO)。电路中引入了过冲、欠冲电压改善模块,用来削减过/欠充电压,互不干扰。过冲电压改善电路将LDO输出电压与参考电压进行比较,过...基于Nuvoton 0.5μm 5 V标准CMOS工艺,设计了一种高稳定性、高瞬态响应、无片外电容低压差线性稳压器(LDO)。电路中引入了过冲、欠冲电压改善模块,用来削减过/欠充电压,互不干扰。过冲电压改善电路将LDO输出电压与参考电压进行比较,过冲状态下开启从LDO输出端到地的快速放电通路,欠冲电压改善电路通过电容耦合获得反映LDO输出电压瞬态变化的采样信号,经反向放大后加速功率管栅极电容放电,进而通过功率管对LDO输出电容充电。仿真结果表明,在TT工艺角下该低压差线性稳压器的空载相位裕度为64.57°,满载相位裕度为62.58°,过冲电压为40 m V,欠冲电压为97.6 m V,线性调整率为0.733‰;负载调整率19μV/m A;电源电压抑制比(PSRR)为-73 d B。展开更多
基金supported by State Key Laboratory of ASIC and Systems of Fudan University and NSF(No.61076027)
文摘A stable LDO using VCCS （voltage control current source） is presented. The LDO is designed and implemented on GF 2P4M 0.35μm CMOS technology. Compared with a previous compensation scheme, VCCS can implement a real stable LDO with a small on-chip capacitor of 1 pF, whose stability is not affected by the variable ESR （equivalent series resistance） of the output capacitor. The unit gain frequency of the LDO loop can achieve 1.5 MHz, improving the transient response. The PSR of the LDO is larger than 45 dB within 0-40 kHz. The static current of the LDO at heavy load of 100 mA is 57 μA and the dropout voltage of the LDO is 150 mV. Experimental results show that a setting time of 10 ks is achieved, and the variation of output voltage is smaller than 35 mV for a 100 mA load step in transient response of the LDO.
文摘基于Nuvoton 0.5μm 5 V标准CMOS工艺,设计了一种高稳定性、高瞬态响应、无片外电容低压差线性稳压器(LDO)。电路中引入了过冲、欠冲电压改善模块,用来削减过/欠充电压,互不干扰。过冲电压改善电路将LDO输出电压与参考电压进行比较,过冲状态下开启从LDO输出端到地的快速放电通路,欠冲电压改善电路通过电容耦合获得反映LDO输出电压瞬态变化的采样信号,经反向放大后加速功率管栅极电容放电,进而通过功率管对LDO输出电容充电。仿真结果表明,在TT工艺角下该低压差线性稳压器的空载相位裕度为64.57°,满载相位裕度为62.58°,过冲电压为40 m V,欠冲电压为97.6 m V,线性调整率为0.733‰;负载调整率19μV/m A;电源电压抑制比(PSRR)为-73 d B。
