Design of a Low Power DSP with Distributed and Early Clock Gating

A novel clock structure of a low-power 16-bit very large instruction word (VLIW) digital signal processor (DSP) was proposed. To improve deterministic clock gating and to solve the drawback of conventional clock gating circuit in high speed circuit, a distributed and early clock gating method was developed on its instruction fetch & decoder unit, its pipelined data-path unit and its super-Harvard memory interface unit. The core was implemented following the Synopsys back-end flow under TSMC (Taiwan Silicon manufacture corporation) 0.18-μm 1.8-V 1P6M process, with a core size of 2 mm×2 mm. Result shows that it can run under 200 MHz with a power performance around 0.3 mW/MIPS. Meanwhile, only 39.7% circuit is active simultaneously in average, compared to its non-gating counterparts.

Rubidium-beam microwave clock pumped by distributed feedback diode lasers

A rubidium-beam microwave clock, optically pumped by a distributed feedback diode laser, is experimentally investigated. The clock is composed of a physical package, optical systems, and electric servo loops. The physical package realizes the microwave interrogation of a rubidium-atomic beam. The optical systems, equipped with two 780-nm distributed feedback laser diodes, yield light for pumping and detecting. The servo loops control the frequency of a local oscillator with respect to the microwave spectrum. With the experimental systems, the microwave spectrum, which has an amplitude of 4 n A and a line width of 700 Hz, is obtained. Preliminary tests show that the clock short-term frequency stability is 7 × 10^-11 at 1 s, and 3 × 10^-12 at 1000 s. These experimental results demonstrate the feasibility of the scheme for a manufactured clock.

Hierarchical distribution network for low skew and high variation-tolerant bufferless resonant clocking

We propose a hierarchical interconnection network with two-phase bufferless resonant clock distribution, which mixes the advantages of mesh and tree architectures.The problems of skew reduction and variation-tolerance in the mixed interconnection network are studied through a pipelined multiplier under a TSMC 65 nm standard CMOS process.The post-simulation results show that the hierarchical architecture reduces more than 75% and 65%of clock skew compared with pure mesh and pure H-tree networks,respectively.The maximum skew in the proposed clock distribution is less than 7 ps under imbalanced loading and PVT variations,which is no more than 1%of the clock cycle of about 760 ps.

Similarities and differences of city-size distributions in three main urban agglomerations of China from 1992 to 2015： A comparative study based on nighttime light data

Comparing the city-size distribution at the urban agglomeration（UA） scale is important for understanding the processes of urban development. However, comparative studies of city-size distribution among China＇s three largest UAs, the Beijing-Tianjin-Hebei agglomeration（BTHA）, the Yangtze River Delta agglomeration（YRDA）, and the Pearl River Delta agglomeration（PRDA）, remain inadequate due to the limitation of data availability. Therefore, using urban data derived from time-series nighttime light data, the common characteristics and distinctive features of city-size distribution among the three UAs from 1992 to 2015 were compared by the Pareto regression and the rank clock method. We identified two common features. First, the city-size distribution became more even. The Pareto exponents increased by 0.17, 0.12, and 0.01 in the YRDA, BTHA, and PRDA, respectively. Second, the average ranks of small cities ascended, being 0.55, 0.08 and 0.04 in the three UAs, respectively. However, the average ranks of large and medium cities in the three UAs experienced different trajectories, which are closely related to the similarities and differences in the driving forces for the development of UAs. Place-based measures are encouraged to promote a coordinated development among cities of differing sizes in the three UAs.

Digital prototype of LLRF system for SSRF

This paper describes a field programming gate array （FPGA） based low level radio frequency （LLRF） prototype for the SSRF storage ring RF system： This prototype includes the local oscillator （LO）, analog front end, digital front end, RF out, clock distributing, digital signal processing and communication functions. All feedback algorithms are performed in FPGA. The long term of the test prototype with high power shows that the variations of the RF amplitude and the phase in the accelerating cavity are less than 1% and 1° respectively, and the variation of the cavity resonance frequency is controlled within 4-10 Hz.

Design and Verification of High-Speed VLSI Physical Design

With the rapid development of deep submicron (DSM) VLSI circuit designs, many issues such as time closure and power consumption are making the physical designs more and more challenging. In this review paper we provide readers with some recent progress of the VLSI physical designs. The recent developments of floorplanning and placement, interconnect effects, modeling and delay, buffer insertion and wire sizing, circuit order reduction, power grid analysis, parasitic extraction, and clock signal distribution are briefly reviewed.

Efficient design of rotary traveling wave oscillator array via geometric programming

This paper presents an efficient method for globally optimizing and automating component sizing for rotary traveling wave oscillator arrays. The lumped equivalent model of transmission lines loaded by inverter pairs is evaluated and posynomial functions for oscillation frequency, power dissipation, phase noise, etc. are formulated using transmission line theory. The re- sulting design problem can be posed as a geometric programJning problem, which can be efficiently solved with a convex opti- mization solver. The proposed method can compute the global optima more efficiently than the traditional iterative scheme and various design problems can be solved with the same circuit model. The globally optimal trade-off curves between competing objectives are also computed to carry out robust designs and quickly explore the design space.

Design and simulation of a standing wave oscillator based PLL

A standing wave oscillator(SWO) is a perfect clock source which can be used to produce a high frequency clock signal with a low skew and high reliability. However, it is difficult to tune the SWO in a wide range of frequencies. We introduce a frequency tunable SWO which uses an inversion mode metal-oxide-semiconductor(IMOS) field-effect transistor as a varactor, and give the simulation results of the frequency tuning range and power dissipation. Based on the frequency tunable SWO, a new phase locked loop(PLL) architecture is presented. This PLL can be used not only as a clock source, but also as a clock distribution network to provide high quality clock signals. The PLL achieves an approximately 50% frequency tuning range when designed in Global Foundry 65 nm 1P9 M complementary metal-oxide-semiconductor(CMOS) technology, and can be used directly in a high performance multi-core microprocessor.