Cryo-CMOS modeling and a 600 MHz cryogenic clock generator for quantum computing applications

The development of large-scale quantum computing has boosted anurgent desire for the advancement of cryogenic CMOS(cryo-CMOS),which is a promising scalable solution for the control and read-out interface of quantum bits.In the current work,180 nm CMOS transistors were characterized and modeled down to 4 K,and the impact oflow-temperature transistor performance variations on circuit designwas also analyzed.Based on the proposed cryogenic model,a 180 nmCMOS-based 450 to 850 MHz clock generator operating at 4 K forquantum computing applications was presented.At the output frequency of 600 MHz,it achieved<4.8 ps RMS jitter with 30 mWpower consumption(with test buffer),corresponding to a−211.6 dBjitter-power FOM,which is suitable for providing a stable clock signalfor the control and readout electronics of scalable quantum computers.

An advanced monolithic digitalized random carrier frequency spread-spectrum clock generator for EMI suppression

A novel monolithic digitalized random carrier frequency modulation spread-spectrum clock generator （RCF-SSCG） is proposed.In this design,the output frequency of the proposed RCF-SSCG changes with the intensity of the capacitive charge and discharge current.Its analytical model is induced and the effect of the modulation parameters on the spread spectrum is numerically simulated and discussed.Compared with other works,this design has the advantages of small size,low power consumption and good robustness.The circuit has been fabricated in a 0.5μm CMOS process and applied to a class D amplifier in which the proposed RCF-SSCG occupies an area of 0.112 mm^2 and consumes 9 mW.The experimental results confirm the theoretical analyses.

A 270-MHz to 1.5-GHz CMOS PLL clock generator with reconfigurable multi-functions for FPGA

A PLL clock generator with reconfigurable multi-functions for FPGA design applications is presented. This clock generator has two configurable operation modes to achieve clock multiplication and phase alignment functions,respectively.The output clock signal has advanced clock shift ability such that the phase shift and duty cycle are programmable.In order to further improve the accuracy of phase alignment and phase shift,a VCO design based on a novel quick start-up technique is proposed.A new delay partition method is also adopted to improve the speed of the post-scale counter,which is used to realize the programmable phase shift and duty cycle.A prototype chip implemented in a 0.13-μm CMOS process achieves a wide tuning range from 270 MHz to 1.5 GHz.The power consumption and the measured RMS jitter at 1 GHz are less than 18 mW and 9 ps,respectively.The settling time is approximately 2μs.

Design and implementation of control system for superconducting RSFQ circuit

The superconducting rapid single flux quantum(RSFQ)integrated circuit is a promising solu-tion for overcoming speed and power bottlenecks in high-performance computing systems in the post-Moore era.This paper presents an architecture designed to improve the speed and power limitations of high-performance computing systems using superconducting technology.Since superconducting microprocessors,which operate at cryogenic temperatures,require support from semiconductor cir-cuits,the proposed design utilizes the von Neumann architecture with a superconducting RSFQ mi-croprocessor,cryogenic semiconductor memory,a room temperature field programmable gate array(FPGA)controller,and a host computer for input/output.Additionally,the paper introduces two key circuit designs:a start/stop controllable superconducting clock generator and an asynchronous communication interface between the RSFQ and semiconductor chips used to implement the control system.Experimental results demonstrate that the proposed design is feasible and effective,provi-ding valuable insights for future superconducting computer systems.

A high speed sampler for sub-sampling IR-UWB receiver

A high speed sampler for a sub-sampling impulse radio UWB receiver is presented. In this design, the sampler uses a time-interleaved topology with a single track and hold circuit, full custom clock generator, and off- set cancelled comparator. These three main blocks are also discussed and analyzed. The circuit was fabricated in 0.13 μm CMOS technology. Measurement results indicate that the sampler achieves a maximum 3 GS/s sampling rate. The power consumption of the sampler is 27 mW under a supply voltage of 1.2 V. The total chip area including pads is 1.4 × 0.97 mm^2.

A time-domain digitally controlled oscillator composed of a free running ring oscillator and flying-adder

A time-domain digitally controlled oscillator （DCO） is proposed. The DCO is composed of a free-running ring oscillator （FRO） and a two lap-selectors integrated flying-adder （FA）. With a coiled cell array which allows uniform loading capacitances of the delay cells, the FRO produces 32 outputs with consistent tap spacing for the FA as reference clocks. The FA uses the outputs from the FRO to generate the output of the DCO according to the control number, resulting in a linear dependence of the output period, instead of the frequency on the digital controlling word input. Thus the proposed DCO ensures a good conversion linearity in a time-domain, and is suitable for time-domain all-digital phase locked loop applications. The DCO was implemented in a standard 0.13μm digital logic CMOS process. The measurement results show that the DCO has a linear and monotonic tuning curve with gain variation of less than 10%, and a very low root mean square period jitter of 9.3 ps in the output clocks. The DCO works well at supply voltages ranging from 0.6 to 1.2 V, and consumes 4 mW of power with 500 MHz frequency output at 1.2 V supply voltage.