This study aims to evaluate the safety status of electrical installations in residential and commercial buildings within the Suame ECG strategic business unit, Ghana, focusing on compliance with international and Ghan...This study aims to evaluate the safety status of electrical installations in residential and commercial buildings within the Suame ECG strategic business unit, Ghana, focusing on compliance with international and Ghanaian wiring standards. The research assesses key factors influencing safety, including the certification of electricians, the quality of cable brands used, proper cable sizing, adherence to wiring color codes, the awareness and use of Residual Current Circuit Breakers (RCCBs), and the protection of earth electrodes. A descriptive research design was utilized, involving extensive field surveys and electrical installation audits. Data were collected using standardized tools and analyzed with SPSS software to evaluate the professional competencies of artisans and their adherence to safety standards. The findings indicate significant safety risks, with 69.7% of electricians lacking proper certification, leading to the widespread use of non-approved cable brands, improper cable sizing, and deviations from wiring color codes. Additionally, deficiencies were found in the awareness and use of RCCBs and the protection of earth electrodes. The study concludes with recommendations to enhance electrical safety, including mandatory certification for electricians, public awareness campaigns, regular inspections, and ongoing training and development programs. These measures are crucial for improving the overall safety and quality of electrical installations in the Suame area, Ghana.展开更多
System-on-a-chips with intellectual property cores need a large volume of data for testing. The large volume of test data requires a large testing time and test data memory. Therefore new techniques are needed to opti...System-on-a-chips with intellectual property cores need a large volume of data for testing. The large volume of test data requires a large testing time and test data memory. Therefore new techniques are needed to optimize the test data volume, decrease the testing time, and conquer the ATE memory limitation for SOC designs. This paper presents a new compression method of testing for intellectual property core-based system-on-chip. The proposed method is based on new split- data variable length (SDV) codes that are designed using the split-options along with identification bits in a string of test data. This paper analyses the reduction of test data volume, testing time, run time, size of memory required in ATE and improvement of compression ratio. Experimental results for ISCAS 85 and ISCAS 89 Benchmark circuits show that SDV codes outperform other compression methods with the best compression ratio for test data compression. The decompression architecture for SDV codes is also presented for decoding the implementations of compressed bits. The proposed scheme shows that SDV codes are accessible to any of the variations in the input test data stream.展开更多
A memory and driving clock efficient design scheme to achieve WCDMA high-speed channel decoder on a single XILINX’ XVC1000E FPGA chip is presented. Using a modified MAP algorithm, say parallel Sliding Window logarith...A memory and driving clock efficient design scheme to achieve WCDMA high-speed channel decoder on a single XILINX’ XVC1000E FPGA chip is presented. Using a modified MAP algorithm, say parallel Sliding Window logarithmic Maximum A Posterior (PSW-log-MAP), the on-chip turbo decoder can decode an information bit by only an average of two clocks per iteration. On the other hand, a high-parallel pipeline Viterbi algorithm is adopted to realize the 256-state convolutional code decoding. The final decoder with an 8×chip-clock (30 72MHz) driving can concurrently process a data rate up to 2 5Mbps of turbo coded sequences and a data rate over 400kbps of convolutional codes. There is no extern memory needed. Test results show that the decoding performance is only 0 2～0 3dB or less lost comparing to float simulation.展开更多
文摘This study aims to evaluate the safety status of electrical installations in residential and commercial buildings within the Suame ECG strategic business unit, Ghana, focusing on compliance with international and Ghanaian wiring standards. The research assesses key factors influencing safety, including the certification of electricians, the quality of cable brands used, proper cable sizing, adherence to wiring color codes, the awareness and use of Residual Current Circuit Breakers (RCCBs), and the protection of earth electrodes. A descriptive research design was utilized, involving extensive field surveys and electrical installation audits. Data were collected using standardized tools and analyzed with SPSS software to evaluate the professional competencies of artisans and their adherence to safety standards. The findings indicate significant safety risks, with 69.7% of electricians lacking proper certification, leading to the widespread use of non-approved cable brands, improper cable sizing, and deviations from wiring color codes. Additionally, deficiencies were found in the awareness and use of RCCBs and the protection of earth electrodes. The study concludes with recommendations to enhance electrical safety, including mandatory certification for electricians, public awareness campaigns, regular inspections, and ongoing training and development programs. These measures are crucial for improving the overall safety and quality of electrical installations in the Suame area, Ghana.
文摘System-on-a-chips with intellectual property cores need a large volume of data for testing. The large volume of test data requires a large testing time and test data memory. Therefore new techniques are needed to optimize the test data volume, decrease the testing time, and conquer the ATE memory limitation for SOC designs. This paper presents a new compression method of testing for intellectual property core-based system-on-chip. The proposed method is based on new split- data variable length (SDV) codes that are designed using the split-options along with identification bits in a string of test data. This paper analyses the reduction of test data volume, testing time, run time, size of memory required in ATE and improvement of compression ratio. Experimental results for ISCAS 85 and ISCAS 89 Benchmark circuits show that SDV codes outperform other compression methods with the best compression ratio for test data compression. The decompression architecture for SDV codes is also presented for decoding the implementations of compressed bits. The proposed scheme shows that SDV codes are accessible to any of the variations in the input test data stream.
文摘A memory and driving clock efficient design scheme to achieve WCDMA high-speed channel decoder on a single XILINX’ XVC1000E FPGA chip is presented. Using a modified MAP algorithm, say parallel Sliding Window logarithmic Maximum A Posterior (PSW-log-MAP), the on-chip turbo decoder can decode an information bit by only an average of two clocks per iteration. On the other hand, a high-parallel pipeline Viterbi algorithm is adopted to realize the 256-state convolutional code decoding. The final decoder with an 8×chip-clock (30 72MHz) driving can concurrently process a data rate up to 2 5Mbps of turbo coded sequences and a data rate over 400kbps of convolutional codes. There is no extern memory needed. Test results show that the decoding performance is only 0 2～0 3dB or less lost comparing to float simulation.
