Asymmetrical Multi-level DC-link Inverter for PV Energy System with Perturb and Observe Based Voltage Regulator and Capacitor Compensator

In this paper, a perturb and observe(P&O) based voltage regulator(POVR) and a capacitor compensator(CC)circuit are proposed for the implementation on 31-level asymmetrical switch-diode based multi-level DC-link(MLDCL) inverter. Since the application of MLDCL in a standalone photovoltaic(PV) system requires constant DC voltages from PV panels, the POVR strategy is deployed to regulate the voltage along with the capability to deliver the maximum power at full load.Boost DC-DC converters are used as the interface between the panels and the inverter for the POVR operation. The results show that POVR is capable of achieving the desired fixed DC voltages even under varying environmental and load conditions,with a steady 230 V at the output. At full load, the standalone system successfully delivers 97.21% of the theoretical maximum power. Additionally, CC is incorporated to mitigate voltage spikes at the output when supplying power to inductive loads.It successfully eliminates the spikes and also reduces the total harmonic distortion(THD) of output current and voltage from more than 10% to less than 5%, as recommended in IEEE 519 standard.

An 11-bit 22-MS/s 0.6 mW SAR ADC with parasitic capacitance compensation

： This paper presents an l 1-bit 22-MS/s 0.6-mW successive approximation register （SAR） analog-to- digital converter （ADC） using SMIC 65-nm low leakage （LL） CMOS technology with a 1.2 V supply voltage. To reduce the total capacitance and core area the split capacitor architecture is adopted. But in high resolution ADCs the parasitic capacitance in the LSB-side would decrease the linearity of the ADC and it is hard to calibrate. This paper proposes a parasitic capacitance compensation technique to cancel the effect with no calibration circuits. Moreover, dynamic circuits are used to minimize the switching power of the digital logic and also can reduce the latency time. The prototype chip realized an 11-bit SAR ADC fabricated in SMIC 65-nm CMOS technology with a core area of 300 × 200 μm2. It shows a sampling rate of 22 MS/s and low power dissipation of 0.6 mW at a 1.2 V supply voltage. At low input frequency the signal-to-noise-and-distortion ratio （SNDR） is 59.3 dB and the spurious-free dynamic range is 72.2 dB. The peak figure-of-merit is 36.4 fJ/conversion-step.

A current-mode DC-DC buck converter with adaptive zero compensation

To achieve fast transient response for a DC-DC buck converter,an adaptive zero compensation circuit is presented.The compensation resistance is dynamically adjusted according to the different output load conditions, and achieves an adequate system phase margin under the different conditions.An improved capacitor multiplier circuit is adopted to realize the minimized compensation capacitance size.In addition,analysis of the small-signal model shows the correctness of the mechanism of the proposed adaptive zero compensation technique.A currentmode DC-DC buck converter with the proposed structure has been implemented in a 0.35μm CMOS process,and the die size is only 800×1040μm;.The experimental results show that the transient undershoot/overshoot voltage and the recovery times do not exceed 40 mV and 30μs for a load current variation from 100 mA to 1 A.