The analytical model for crosstalk noise of current-mode signaling in coupled RLC interconnects of VLSI circuits

With the continuous advancement of semiconductor technology, the interconnects crosstalk has had a great influence on the performances of VLSI circuits. To date, most of the research about the interconnects of VLSI circuits focus on the voltage-mode signaling （VMS） scheme while the current-mode signaling （CMS） scheme is rarely analyzed. First of all, an equivalent circuit model of two-line coupled interconnects is presented in this paper, which is applicable to both the CMS and VMS schemes. The coupling capacitive and mutual inductive are taken into account in the equivalent circuit model. Secondly, the output noise of CMS and VMS schemes are investigated in the paper according to the decoupling technique and A B CD parameter matrix approach at local level, intermediate level and global level, respectively. Moreover, the experimental results show that the CMS interconnects have lesser noise peak, noise width and noise amplitude than the VMS interconnects in the same cases, and the CMS scheme is especially suitable for the global interconnects communication of VLSI circuits. It is found that the results obtained by A B CD parameter matrix approach are in good accordance with the simulation results of the advanced design system.

Progress and Research on Interconnects Crosstalk in Deep Submicron Technology

As develops in deep sub micron designs,the interconnect crosstalk becomes much more serious.Espe cially, the coupling inductance can not be ignored in gigahertz designs.So shield insertion is an efficient technique to reduce the inductive noise.In this paper,the characteristics of on chip mutual inductance (as well as self) for coplanar,micro stripline and stripline structures are introduced first.Then base on the coplanar interconnect structures,the effective coupling K eff model and the RLC explicit noise model are proposed respectively.The results of experiments show that these two models both have high fidelity.

FDTD based transition time dependent crosstalk analysis for coupled RLC interconnects

The performance of high density chips operating in the GHz range is mostly affected by on-chip interconnects. The interconnect delay depends on many factors, a few of them are inputs toggling patterns, line ＆ coupling parasitics, input rise/fall time and source/load characteristics. The transition time of the input is of prime importance in high speed circuits. This paper addresses the FDTD based analysis of transition time effects on functional and dynamic crosstalk. The analysis is carried out for equal and unequal transition times of coupled inputs. The analysis of the effects of unequal rise time is equally important because practically, it is quite common to have mismatching in the rise time of the signals transmitting through different length wires. To demonstrate the effects, two distributed RLC lines coupled inductively and capacitively are taken into consideration. The FDTD technique is used because it gives accurate results and carries time domain analysis of coupled lines. The number of lumps in SPICE simulations is considered the same as those of spatial segments. To validate the FDTD computed results, SPICE simulations are run and results are compared. A good agreement of the computed results has been observed with respect to SPICE simulated results. An average error of less than 3.2% is observed in the computation of the performance parameters using the proposed method.