Variability-Based Models for Testability Analysis of Frameworks

Frameworks are developed to capture the recurring design practices in terms of skeletons of software subsystems/ systems. They are designed ‘abstract’ and ‘incomplete’ and are designed with predefined points of variability, known as hot spots, to be customized later at the time of framework reuse. Frameworks are reusable entities thus demand stricter and rigorous testing in comparison to one-time use application. It would be advisable to guaranty the production of high quality frameworks without incurring heavy costs for their rigorous testing. The overall cost of framework development may be reduced by designing frameworks with high testability. This paper aims at discussing various metric models for testability analysis of frameworks in an attempt to having quantitative data on testability to be used to plan and monitor framework testing activities so that the framework testing effort and hence the overall framework development effort may be brought down. The models considered herein particularly consider that frameworks are inherently abstract and variable in nature.

A New Virtual Disk Mapping Method for the Cloud Desktop Storage Client

Integration of the cloud desktop and cloud storage platform is urgent for enterprises. However, current proposals for cloud disk are not satisfactory in terms of the decoupling of virtual computing and business data storage in the cloud desktop environment. In this paper, we present a new virtual disk mapping method for cloud desktop storage. In Windows, compared with virtual hard disk method of popular cloud disks, the proposed implementation of client based on the virtual disk driver and the file system filter driver is available for widespread desktop environments, especially for the cloud desktop with limited storage resources. Further more, our method supports customizable local cache storage, resulting in userfriendly experience for thinclients of the cloud desktop. The evaluation results show that our virtual disk mapping method performs well in the readwrite throughput of different scale files.

Screen printing fabricating patterned and customized full paper-based energy storage devices with excellent photothermal,self-healing,high energy density and good electromagnetic shielding performances

Supercapacitors are favored by researchers because of their high power density,especially with the acceleration of people’s life rhythm.However,their energy density,especially from the point of view of the whole energy storage device,is far lower than that of commercial batteries.In this work,a kind of customizable full paper-based supercapacitor device with excellent self-healing ability is fabricated by simple and low-cost screen printing,electropolymerization and dip coating methods.The resultant separatorfree supercapacitor device exhibits both ultrahigh gravimetric and areal specific energy(power)densities of 39 Wh kg^(-1)(69 k W kg^(-1))and 692μWh cm^(-2)(236 m W cm^(-2)),achieving excellent supercapacitor performance.Notably,the addition of vitrimers endows the whole device with outstanding self-healing properties,which is helpful for enhancing the adaptability of the device to the environment.In addition,this kind of paper-based device also displays good photothermal and electromagnetic shielding performances.These striking features make paper matrix composites attractive in the fields of supercapacitors,medical photothermal treatment and electromagnetic shielding.

Recent status and future perspectives of ultracompact and customizable micro-supercapacitors

Ultracompact and customizable micro-supercapacitors(MSCs)are highly demanded for powering microscale electronics of 5G and Internet of Things technologies.So far,tremendous efforts have been concentrated on fabricating high-performance MSCs;however,compatible fabrication and monolithic integration of MSCs with microelectronic systems still remains a huge challenge taking into full consideration the factors such as electrode film fabrication,high-resolution microelectrode pattern,and electrolyte precise deposition.In this review,we summarize the recent advances of ultrasmall and integrated MSCs with tunable performance and customizable function,including key microfabrication technologies for patterning microelectrodes with superior resolution,precise deposition of customized electrolytes in an extremely small space,and feasible strategies for improving electrochemical performance by constructing thick microelectrodes and special electrode structure.Finally,the related challenges and key prospects of ultracompact and customizable MSCs,including compatible microfabrication methods for electrode materials and films,patterning microelectrodes,customizing shape-conformable electrolytes,performance optimization,and efficient integration with microelectronic systems,are put forward for further promoting their practical application.

VPOT:A Customizable Variant Prioritization Ordering Tool for Annotated Variants

Next-generation sequencing(NGS) technologies generate thousands to millions of genetic variants per sample.Identification of potential disease-causal variants is labor intensive as it relies on filtering using various annotation metrics and consideration of multiple pathogenicity prediction scores.We have developed VPOT(variant prioritization ordering tool),a python-based command line tool that allows researchers to create a single fully customizable pathogenicity ranking score from any number of annotation values,each with a user-defined weighting.The use of VPOT can be informative when analyzing entire cohorts,as variants in a cohort can be prioritized.VPOT also provides additional functions to allow variant filtering based on a candidate gene list or by affected status in a family pedigree.VPOT outperforms similar tools in terms of efficacy,flexibility,scalability,and computational performance.VPOT is freely available for public use at Git Hub(https://github.com/VCCRI/VPOT/).Documentation for installation along with a user tutorial,a default parameter file,and test data are provided.

Solvent-free Synthesis of Flowable Carbon Clusters with Customizable Size and Tunable Optical Performance

We propose a rapid and solvent-flee route for synthesizing luminous carbon clusters by controlling carbonization of polyethylene glycol （PEG）. This approach does not involve solvents yet uses the precursor itself as suspend- ing medium, thus features mild and green chemistry, and also enables the formation of uniform-sized carbon clus- ters, of which the diameter can be easily tuned from 0.7 to 3.5 nm via control of reaction time. In term of the di- mension, the resultants are denoted as sub-nano carbon clusters （SNCs） and carbon dots （CDs）, respectively. Bene- fiting from surface anchored PEG segments, both of the two show favorable flowability at room temperature and excellent solubility in aqueous and organic solvents. Comparison of their optical performances and structures re- veals that they share the same chromophores. Particularly, the SNCs demonstrate robust photo- and pH-stable pho- toluminescence and can be directly applied to cell-imaging regarding to its prominent biocompatibility. Moreover, its quantum yield （5.5%）, which is approximately 3 times higher than that of CDs （1.5%）, can be dramatically en- hanced to 18.8% by facile chemical reduction. We anticipate that these PEG derivatives marked with easy synthesis, controllable optical performances and excellent physical properties will be highly appealing in future applications.

HW/SW Co-optimization for Stencil Computation：Beginning with a Customizable Core

Energy efficiency is one of the most important issues for High Performance Computing（HPC） today.Heterogeneous HPC platform with some energy-efficient customizable cores（as application-specific accelerators）is believed as one of the promising solutions to meet ever-increasing computing needs and to overcome power density limitations. In this paper, we focus on using customizable processor cores to optimize the typical stencil computations—— the kernel of many high-performance applications. We develop a series of effective software/hardware co-optimization strategies to exploit the instruction-level and memory-computation parallelism,as well as to decrease the energy consumption. These optimizations include loop tiling, prefetching, cache customization, Single Instruction Multiple Data（SIMD）, and Direct Memory Access（DMA）, as well as necessary ISA extensions. Detailed tests of power-efficiency are given to evaluate the effect of all these optimizations comprehensively. The results are impressive： the combination of these optimizations has improved the application performance by 341% while the energy consumption has been decreased by 35%; a preliminary comparison with X86, GPU, and FPGA platforms also showed that the design could achieve an order of magnitude higher performance efficiency. We believe this work can help understand sources of inefficiency in general-purpose chips and can be used as a beginning to customize an energy efficient CMP for further improvement.