Digital down converter （DDC） is the main part of the next generation high frequency （HF） radar. In order to realize the single chip integrations of digital receiver hardware in the next generation HF Radar, a new ...Digital down converter （DDC） is the main part of the next generation high frequency （HF） radar. In order to realize the single chip integrations of digital receiver hardware in the next generation HF Radar, a new design for DDC by using FPGA is presented. Some important and practical applications are given in this paper, and the result can prove the validity. Because we can adjust the parameters freely according to our need, the DDC system can be adapted to the next generation HF radar system.展开更多
The relationship between the hardware requirement of digital down converters（DDCs）in ultra-low symbol rate receivers and the word length is studied.Through analyzing the impact of word length selection to the system...The relationship between the hardware requirement of digital down converters（DDCs）in ultra-low symbol rate receivers and the word length is studied.Through analyzing the impact of word length selection to the system performance,a modified scheme is presented to decline the resource consumption without too much degradation on the signal to noise ratio（SNR）.Theoretical analysis and numerical results demonstrate that compared to the traditional design,the proposed scheme could save dozens of memory resources.The scheme also includes some selectable parameters to achieve desired performance in various circumstances.Different from previous work in DDCs that concentrates mostly on the structure design,this paper considers special applications such as ultra-low symbol rate receivers.展开更多
以郑西客运专线为工程背景,分析DDC(Down Hole Dy-nam ic Compaction,简称DDC技术)桩法(孔内深层强夯技术)控制深厚湿陷性黄土地基工后沉降的机理及其技术优势,提出DDC桩法工后沉降计算及参数选取模式,结合具体工点进行设计分析,为铁路...以郑西客运专线为工程背景,分析DDC(Down Hole Dy-nam ic Compaction,简称DDC技术)桩法(孔内深层强夯技术)控制深厚湿陷性黄土地基工后沉降的机理及其技术优势,提出DDC桩法工后沉降计算及参数选取模式,结合具体工点进行设计分析,为铁路客运专线的设计提供参考。展开更多
文摘Digital down converter （DDC） is the main part of the next generation high frequency （HF） radar. In order to realize the single chip integrations of digital receiver hardware in the next generation HF Radar, a new design for DDC by using FPGA is presented. Some important and practical applications are given in this paper, and the result can prove the validity. Because we can adjust the parameters freely according to our need, the DDC system can be adapted to the next generation HF radar system.
基金Supported by the National Natural Science Foundation of China(60972018)
文摘The relationship between the hardware requirement of digital down converters（DDCs）in ultra-low symbol rate receivers and the word length is studied.Through analyzing the impact of word length selection to the system performance,a modified scheme is presented to decline the resource consumption without too much degradation on the signal to noise ratio（SNR）.Theoretical analysis and numerical results demonstrate that compared to the traditional design,the proposed scheme could save dozens of memory resources.The scheme also includes some selectable parameters to achieve desired performance in various circumstances.Different from previous work in DDCs that concentrates mostly on the structure design,this paper considers special applications such as ultra-low symbol rate receivers.
