Digital elevation model(DEM)matching techniques have been extended to DEM deformation detection by substituting a robust estimator for the least squares estimator,in which terrain changes are treated as gross errors.H...Digital elevation model(DEM)matching techniques have been extended to DEM deformation detection by substituting a robust estimator for the least squares estimator,in which terrain changes are treated as gross errors.However,all existing methods only emphasise their deformation detecting ability,and neglect another important aspect:only when the gross error can be detected and located,can this system be useful.This paper employs the gross error judgement matrix as a tool to make an in-depth analysis of this problem.The theoretical analyses and experimental results show that observations in the DEM matching algorithm in real applications have the ability to detect and locate gross errors.Therefore,treating the terrain changes as gross errors is theoretically feasible,allowing real DEM deformations to be detected by employing a surface matching technique.展开更多
The delta-sigma converter is one of the high speed and resolution analog-to-digital modulators. Its implementation needs the low oversampling technique and the multi-bit D/A converter. The noise induced by the multi-b...The delta-sigma converter is one of the high speed and resolution analog-to-digital modulators. Its implementation needs the low oversampling technique and the multi-bit D/A converter. The noise induced by the multi-bit D/A converter becomes one of the key factors deteriorating the signal-to-noise rate of the delta-sigma A/D converter. A novel structure with signal unity transfunction, dynamic element matching(DEM) and noise-shaping is discussed. The method is investigated to design converter based on the proposed structure. The behavior simulation indicates that the structure and the design method are feasible.展开更多
A 2.5 GS/s 14-bit D/A converter(DAC) with 8 to 1 MUX is presented. This 14-bit DAC uses a "5+9"segment PMOS current-steering architecture. A bias circuit which ensures the PMOS current source obtains a larger out...A 2.5 GS/s 14-bit D/A converter(DAC) with 8 to 1 MUX is presented. This 14-bit DAC uses a "5+9"segment PMOS current-steering architecture. A bias circuit which ensures the PMOS current source obtains a larger output impedance under every PVT(process, source voltage and temperature) corner is also presented. The8 to 1 MUX has a 3 stage structure, and a proper timing sequence is designed to ensure reliable data synthesis. A DEM function which is merged with a "5-31"decoder is used to improve the DAC's dynamic performance. This DAC is embedded in a 2.5 GHz direct digital frequency synthesizer(DDS) chip, and is implemented in a 0.18 m CMOS technology, occupies 4.86 2. 28 mm-2 including bond pads(DAC only), and the measured performance is SFDR 〉 40 d B(with and without DEM) for output signal frequency up to 1 GHz. Compared with other present published DACs with a non-analog-resample structure(means return-to-zero or quad-switch structure is unutilized),this paper DAC's clock frequency(2.5 GHz) and higher output frequency SFDR(〉 40 d B, up to 1 GHz) has some competition.展开更多
基金This research is supported by the National High Technology Plan(863)of the People’s Republic of China,Project No.2009AA12Z207.
文摘Digital elevation model(DEM)matching techniques have been extended to DEM deformation detection by substituting a robust estimator for the least squares estimator,in which terrain changes are treated as gross errors.However,all existing methods only emphasise their deformation detecting ability,and neglect another important aspect:only when the gross error can be detected and located,can this system be useful.This paper employs the gross error judgement matrix as a tool to make an in-depth analysis of this problem.The theoretical analyses and experimental results show that observations in the DEM matching algorithm in real applications have the ability to detect and locate gross errors.Therefore,treating the terrain changes as gross errors is theoretically feasible,allowing real DEM deformations to be detected by employing a surface matching technique.
基金National Natural Science Foundation of China(50677014)Doctoral Special Found of Ministry of Education(20060532016)+2 种基金Natural Science Foundation of Hunan Province(06JJ2024)Program for New CenturyExcellent Talents in University(NCET-04-0767)Found of Hunan Education depart ment(05C141)
文摘The delta-sigma converter is one of the high speed and resolution analog-to-digital modulators. Its implementation needs the low oversampling technique and the multi-bit D/A converter. The noise induced by the multi-bit D/A converter becomes one of the key factors deteriorating the signal-to-noise rate of the delta-sigma A/D converter. A novel structure with signal unity transfunction, dynamic element matching(DEM) and noise-shaping is discussed. The method is investigated to design converter based on the proposed structure. The behavior simulation indicates that the structure and the design method are feasible.
基金Project supported by the National Natural Science Foundation of China(Nos.61006027,61176030)the Research Foundation of Key Laboratory of Analog Integrated Circuit(Nos.9140C0902120C09034,9140c090204130c09042)the Fundamental Research Funds for the Central Universities of China(No.ZYGX2012J003)
文摘A 2.5 GS/s 14-bit D/A converter(DAC) with 8 to 1 MUX is presented. This 14-bit DAC uses a "5+9"segment PMOS current-steering architecture. A bias circuit which ensures the PMOS current source obtains a larger output impedance under every PVT(process, source voltage and temperature) corner is also presented. The8 to 1 MUX has a 3 stage structure, and a proper timing sequence is designed to ensure reliable data synthesis. A DEM function which is merged with a "5-31"decoder is used to improve the DAC's dynamic performance. This DAC is embedded in a 2.5 GHz direct digital frequency synthesizer(DDS) chip, and is implemented in a 0.18 m CMOS technology, occupies 4.86 2. 28 mm-2 including bond pads(DAC only), and the measured performance is SFDR 〉 40 d B(with and without DEM) for output signal frequency up to 1 GHz. Compared with other present published DACs with a non-analog-resample structure(means return-to-zero or quad-switch structure is unutilized),this paper DAC's clock frequency(2.5 GHz) and higher output frequency SFDR(〉 40 d B, up to 1 GHz) has some competition.