2.5Gb/s Monolithic IC of Clock Recovery,Data Decision,and 1∶4 Demultiplexer

A high integrated monolithic IC, with functions of clock recovery, data decision, and 1 ： 4 demultiplexer,is implemented in 0.25μm CMOS process for 2.5Gb/s fiber-optic communications. The recovered and frequency divided 625MHz clock has a phase noise of -106.26dBc/Hz at 100kHz offset in response to a 2.5Gb/s PRBS input data （2^31-1）. The 2.5Gb/s PRBS data are demultiplexed to four 625Mb/s data. The 0.97mm× 0.97mm IC consumes 550mW under a single 3.3V power supply （not including output buffers）.

20Gb/s 1∶2 Demultiplexer in 0.18μm CMOS

A 1 ：2 demultiplexer is designed and realized in standard 0. 18μm CMOS technology. A novel high-speed and low-voltage latch is used to realize the core circuit cell. Compared to the traditional source-coupled FET logic structure latch, its power supply voltage is lower and the speed is faster. In addition, the negative feedback is used in the buffer circuit to widen its bandwidth. Measurement results show that the chip can work at the data rate of 20Gb/ s. The supply voltage is 1.8V and the current,including the buffer circuit, is 72mA.

A kind of low-power 10 Gbit/s CMOS 1∶4 demultiplexer

A 10 Gbit/s 1：4 demultiplexer（DEMUX） fabricated in 0. 18 μm CMOS （complementary metal-oxidesemiconductor transistor） technology for optical-fiber-link is presented. The system is constructed in tree-type structure and it includes a high-speed 1 ： 2 DEMUX, two low-speed 1 ： 2 DEMUXs, a divider, and input and output buffers for data and dock. To improve the circuit performance and reduce the power consumption, a latch structure with a common-gate topology and a single clock phase is employed in the high-speed 1 ： 2 DEMUX and the 5 GHz 1 ： 2 on-chip frequency divider, while dynamic CMOS logic is adopted in the low-speed l ： 2 DEMUXs. Measured results at 10 Gbit/s by 23^31 -1 pseudo random bit sequences （PRBS） via on-wafer testing indicate that it can work well with a power dissipation of less than 100 mW at 1.8 V supply voltage. The die area of the DEMUX is 0. 65 mm × 0. 75 mm.

12Gb/s 0.25μm CMOS Low-Power 1∶4 Demultiplexer

A low power 12Gb/s single-stage 1 ： 4 demultiplexer （DEMUX） applied in SONET OC-192 is realized in TSMC＇s mix-signal 0. 25μm CMOS. All of the circuits are in source coupled FET logic （SCFL） to achieve as high a speed as possible and suppress common mode distortions. This DEMUX is featured for achieving singlestage demultiplexing by using a quarter-rate IQ clock. This method not only reduces the components of the DEMUX but also lowers its power dissipation. The fabricated DEMUX operates error free at 12Gb/s by 231 - 1 pseudorandom bit sequences in on-wafer testing. The chip size is 0. 9mm × 0.9mm and the power dissipation is only 210mW with a single 2.5V supply.

20 Gbit/s 1∶2 demultiplexer of low-power using 0.18 μm CMOS

A 1 ： 2 demultiplexer（DEMUX） that is fabricated using 0. 18 μm CMOS （complementary metaloxide-semiconductor transistor） technology is presented. The DEMUX consists of a master-slave-slave, masterslave D flip-flops and output buffers. The D flip-flop employs a dynamic-loading structure and common-gate topology with single clock phase for the bias transistors. The dynamic-loading structure can make the circuit work faster because it decreases the charge/discharge time of the output node, and it consumes lower power because its working current is in a switch mode. In addition, the positive feedback loop, which is made up of a cross-coupled transistor pair in the latch, speeds up the circuit. Measurement results at 20 Gbit/s 2^23 - 1 pseudo random bit sequence （PRBS） via on-wafer testing show that the 1： 2 DEMUX can operate well. The power dissipation is 108 mW with the area of 475μm×578μm.

10 Gbit/s 0.25μm CMOS 1∶4 demultiplexer

A 10 Gbit/s (STM-64, OC-192) 1:4 demultiplexer (DEMUX) with 4-phase clock wasachieved in TSMC's standard 0.25 μm complementary metal-oxide-semiconductor (CMOS) technique. Allof the circuits are in source coupled FET logic (SCFL) to achieve as high as possible speed andsuppress common mode distortions. This DEMUX is featured by constant-delay buffers to generate a4-phase clock and adjust skews of the four channel outputs. The fabricated DEMUX operates error freeat 10 Gbit/s by 2^(31) -1 pseudorandom bit sequences (PRBS) via on-wafer testing. The measured rootmean square (rms) jitter, rising and failing edge of the eye-diagram are 11, 123 and 137 ps,respectively. The chip size is 0.9 mm x 1.2 mm and the power dissipation is 550 mW with a 3. 3 Vsupply.

Semi-vectorial analysis of a compact wavelength demultiplexer based on the tapered multimode interference coupler

Based on a parabolically tapered multimode interference （MMI） coupler with a deep-etched SiO2/SiON rib waveguide, a compact wavelength demultiplexer operating at 1.30 and 1.55 μm wavelengths is proposed and analysed by using three-dimensional semi-vectorial finite-difference beam propagation method （3D-SV-FD-BPM）. The results show that a MMI section of 330.0 μm in length, which is only 76% length of a straight MMI coupler, is achieved with the contrasts of 42.3 and 39.2dB in quasi-TE mode, and 38.4 and 37.8dB in quasi-TM mode at wavelengths 1.30 and 1.55μm, respectively, and the insertion losses below 0.2dB at both wavelengths and in both polarization states, The alternating direction implicit algorithm with the Crank-Nicholson scheme is applied to the discretization of the 3D-SV-FD-BPM formulation along the longitudinal direction. Moreover, a modified FD scheme is constructed to approximate the resulting equations along the transverse directions, in which the discontinuities of the derivatives of magnetic field components Hy and Hx along the vertical and horizontal interfaces, respectively, are involved.

Bound in continuum states and induced transparency in mesoscopic demultiplexer with two outputs

We investigate the electronic transport in a simple mesoscopic cross structure made of two wires(stubs)grafted at the same point along a quantum waveguide.We show that the structure may exhibit important phenomena such as bound in continuum(BIC)states.These states are transformed into electromagnetically induced transparency(EIT)resonance by detuning slightly the lengths of the stubs.The last phenomenon is used to propose and study a mesoscopic demultiplexer device with an input waveguide and two output waveguides.We give closed-form expressions of the geometrical parameters that allow a selective transfer of a given state in the first waveguide without perturbing the second waveguide.The effect of temperature on the transmission resonances is also examined by using Landauer-Büttiker formula.The analytical results of the dispersion relation and transmission and reflection coefficient are obtained using the Green's function method.

Designing thermal demultiplexer: Splitting phonons by negative mass and genetic algorithm optimization

We propose the concept of thermal demultiplexer, which can split the heat flux in different frequency ranges intodifferent directions. We demonstrate this device concept in a honeycomb lattice with dangling atoms. From the view ofeffective negative mass, we give a qualitative explanation of how the dangling atoms change the original transport property.We first design a two-mass configuration thermal demultiplexer, and find that the heat flux can flow into different ports incorresponding frequency ranges roughly. Then, to improve the performance, we choose the suitable masses of danglingatoms and optimize the four-mass configuration with genetic algorithm. Finally, we give out the optimal configuration witha remarkable effect. Our study finds a way to selectively split spectrum-resolved heat to different ports as phonon splitter,which would provide a new means to manipulate phonons and heat, and to guide the design of phononic thermal devices inthe future.

Erratum to“Designing thermal demultiplexer:Splitting phonons by negative mass and genetic algorithm optimization”

Equations(8)and(9)in the original paper[Chin.Phys.B 30036301(2021)]are corrected.

High-performance and fabrication friendly polarization demultiplexer

A compact and fabrication friendly polarization demultiplexer(P-DEMUX) is proposed and characterized to enable wavelength-division-multiplexing and polarization-division-multiplexing simultaneously. The proposed structure is composed of a polarization-selective microring resonator in ultrathin waveguide and two bus channels in the silicon nitridesilica-silicon horizontal slot waveguides. In the slot waveguide, the transverse electric(TE) mode propagates through the silicon layer, while the transverse magnetic(TM) mode is confined in the slot region. In the designed ultra-thin waveguide, the TM mode is cut-off. The effective indexes of the TE modes for ultrathin and slot waveguides have comparable values. Thanks for these distinguishing features, the input TE mode can be efficiently filtered through the ultra-thin microring at the resonant wavelength, while the TM mode can directly output from the through port. Simulation results show that the extinction ratio of the proposed P-DEMUX for TE and TM modes are 33.21 dB and 24.97 dB, and the insertion losses are 0.346 dB and 0.324 dB, respectively, at the wavelength of 1551.64 nm. Furthermore, the device shows a broad bandwidth(> 100 nm) for an extinction ratio(ER) of > 20 dB. In addition, the proposed P-DEMUX also has a good fabrication tolerance for the waveguide width variation of-20 nm≤ △w_(g)≤ 20 nm and the microring width variation of -20 nm≤ △w_(r) ≤20 nm for a low insertion loss of < 0.75 dB and low ER of <-18 dB.

Optical Arithmetic Operation Using Optical Demultiplexer

Using Terahertz Optical Asymmetric Demultiplexer (TOAD) based switch we have designed all-optical parallel half adder and full adder. The approach to design this all-optical arithmetic circuit not only enhances the computational speed but also is capable of synthesizing light as input to produce desire output. The main advantage of parallel circuit is synchronization of input which is not required. All the circuits are designed theoretically and verified through numerical simulations.

All-Optical 3:8 Decoder with the Help of Terahertz Optical Asymmetric Demultiplexer

An all-optical 3:8 decoder unit with the help of terahertz optical asymmetric demultiplexer (TOAD) is proposed. The all-optical 3:8 decoder unit with a set of all-optical full-adders and optical exclusive-ORs (XORs), can be used to perform a fast central processor unit using optical hardware components. We try to exploit the advantages of TOAD-based optical switch to design an integrated all-optical circuit which can perform decoding of signal. A theoretical model is presented and verified through numerical simulation. The new method promises both higher processing speed and accuracy. The model can be extended for studying more complex all-optical circuit of enhanced functionality in which decoder is the basic building block. The operation of the proposed circuit is parallel in nature. The impact of the switching energy with small signal gain and variation of extinction ratio and contrast ration with control pulse energy of the switching outcome is explored and assessed by means of numerical simulations.

Design of 2-to-4 All-Optical Decoder with the Help of Terahertz Optical Asymmetric Demultiplexer

An all-optical 2-to-4 decoder unit with the assist of terahertz optical asymmetric demultiplexer (TOAD) is presented. The all-optical 2-to-4 decoder with a set of all-optical switches is designed which can be used to achieve a high-speed central processor unit using optical hardware. The unique output lines can be used for all-optical header processing. We attempt to develop an integrated all-optical circuit which can perform decoding of signal. This scheme is very simple and flexible for performing different logic operation and to design advanced complex logic. Simulated results are confirming the described methods.

On-chip terahertz orbital angular momentum demultiplexer

The terahertz regime is widely recognized as a fundamental domain with significant potential to address the demands of next-generation wireless communications.In parallel,mode division multiplexing based on orbital angular momentum(OAM)shows promise in enhancing bandwidth utilization,thereby expanding the overall communication channel capacity.In this study,we present both theoretical and experimental demonstrations of an on-chip terahertz OAM demultiplexer.This device effectively couples and steers seven incident terahertz vortex beams into distinct high-quality focusing surface plasmonic beams,and the focusing directions can be arbitrarily designated.The proposed design strategy integrates space-to-chip mode conversion,OAM recognition,and on-chip routing in a compact space with subwavelength thickness,exhibiting versatility and superior performance.

A novel DWDM inter leaver scheme based on phased-array wavelength demultiplexer with multimode interference couplers

A novel integrated dense wavelength division multiplexing interleaver scheme is presented based on phased-array (PHASAR) wavelength demultiplexer with multimode interference (MMI) couplers. MMI-PHASAR interleaver with simple structure and compact si/e can reali/e narrow channel spacing through simple design procedure. And it is convenient for integration with integrated planar waveguide multiplexer/demultiplexers. A 25/50-GHz MMI-PHASAR interleaver is designed and the transmission characteristic is investigated by beasu propagation method.

A flat-topped etched diffraction grating demultiplexer with low polarization-dependent loss using a tapered MMI structure

A flat-topped etched diffraction grating (EDG) demultiplexer with a low polarization-dependent loss (PDL) is designed. A design and simulation method based on the method of moment (MoM) is proposed. A 65-channcl EDG demultiplexer with channel spacing of 100 GHz is considered as a design example. A tapered multi-mode interferometer (MMI) is used to flatten the passband of the EDG demultiplexer. The numerical results show that the exit width of the tapered waveguide impacts the loss of the TE case more than that of the TM case. Based on this fact, the exit width of the taper is optimized to obtain the lowest PDL. The tapering angle is also optimized where the minimal ripple is obtained. The designed EDG demultiplexer has an excellent flat-topped spectral response and a very low PDL.

All-optical prefix tree adder with the help of terahertz optical asymmetric demultiplexer

We propose and describe an all-optical prefix tree adder with the help of a terahertz optical asymmetric demultiplexer （TOAD） using a set of optical switches. The prefix tree adder is useful in compound adder implementation. It is preferred over the ripple carry adder and the carry lookahead adder. We also describe the principle and possibilities of the all-optical prefix tree adder. The theoretical model is presented and verified through numerical simulation. The new method promises higher processing speed and accuracy. The model can be extended for studying more complex all-optical circuits of enhanced functionality in which the prefix tree adder is the basic building block.

2-channel all optical demultiplexer based on photonic crystal ring resonator

In this paper, we proposed a 2-channel demultiplexer based on photonic crystal ring resonator （PCRR）. For performing wavelength selection, we used two ring resonators, two different wavelengths were obtained by using two resonant rings with different values for the radius of dielectric rods. All the simulations and calculations have been done using Rsoft Photonic CAD software, which employs finite difference time domain （FDTD） method. The output channels were respectively at 1590.8 and 1593.8nm, correspondingly had the quality factors of 7954 and 3984, the crosstalk values of -22 and -11 dB separately. The total footprint of our proposed structure is 681.36 μm2. Results suggest that 2-channels in the proposed structure are characterized with high transmission efficiency and low band width, resulting in a very sharp output spectrum and high quality factor values.

Terahertz optical asymmetric demultiplexer based tree-net architecture for all-optical conversion scheme from binary to its other 2^n radix based form

To exploit the parallelism of optics in data processing, a suitable number system and an efficient encoding/decoding scheme for handling the data are very essential. In the field of optical computing and parallel information processing, several number systems like binary, quaternary, octal, hexadecimal, etc. have been used for different arithmetic and algebraic operations. Here, we have proposed an all-optical conversion scheme from its binary to its other 2^n radix based form with the help of terahertz optical asymmetric demultiplexer （TOAD） based tree-net architecture.