MIMO-DFE(Multiple-Input-Multiple-Output Decision Feedback Equalizer) based receiver architectures are researched recently to detect signals in BLAST(Bell laboratories LAyered Space-Time) over frequency-selective chann...MIMO-DFE(Multiple-Input-Multiple-Output Decision Feedback Equalizer) based receiver architectures are researched recently to detect signals in BLAST(Bell laboratories LAyered Space-Time) over frequency-selective channels. Due to their recursive structure, these receivers may suffer from error propagation which results in an overall mean square error degradation. An MIMO-DFE based BLAST receiver with limited error propagation to combat frequencyselective channel is proposed, which employs both norm constraint on feedback filter taps and soft decision device. Simulation results show that the proposed receiver outperforms conventional ones in various frequency selective channels.展开更多
A 6.25 Gbps SerDes core used in the high signed based on the OIF-CEI-02.0 standard. To speed backplane communication receiver has been decounteract the serious Inter-Syrmbol-Interference (ISI), the core employed a h...A 6.25 Gbps SerDes core used in the high signed based on the OIF-CEI-02.0 standard. To speed backplane communication receiver has been decounteract the serious Inter-Syrmbol-Interference (ISI), the core employed a half-rate four-tap decision feedback equalizer (DFE). The equalizer used the Signsign least mean-squared (SS-LMS) algorithm to realize the coefficient adaptation. An automatic gain control (AGC) amplifier with the sign least mean-squared (S-LMS) algorithm has been used to compensate the transmission media loss. To recover the clock signal from the input data serial and provide for the DFE and AGC, a bang-bang clock recovery (BB-CR) is adopted. A third order phase loop loek (PLL) model was proposed to predict characteristics of the BB-CR. The core has been verified by behavioral modeling in MATLAB. The results indicate that the core can meet the specifications of the backplane receiver. The DFE recovered data over a 34" FR-4 backplane has a peak-to-peak jitter of 17 ps, a horizontal eye opening of 0.87 UI, and a vertical eye opening of 500 mVpp.展开更多
This paper evaluates the effect of decision feedback equalizer( DFE) error propagation for400 Gb/s Ethernet( 400 GbE) electrical link in order to propose some effective methods to improve bit error rate( BER). First,a...This paper evaluates the effect of decision feedback equalizer( DFE) error propagation for400 Gb/s Ethernet( 400 GbE) electrical link in order to propose some effective methods to improve bit error rate( BER). First,an analytical model for DFE burst error length distribution is proposed and simulated based on a NRZ electrical link in which a 5-tap DFE combined with a multiple-tap feed forward equalizer( FFE) is included. Then,a detailed derivation for BER considering DFE error propagation is given based on the distribution of burst error run length and the BER performance with and without forward error correction( FEC) is simulated too. After that,this paper investigates several MUX-based FEC interleaving methods including their complexity and latency in order to improve BER further. At last,three FEC interleaving schemes are compared not only in interleaving gain,but also in hardware complexities and latencies. Simulation results show that pre-interleave bit muxing can obtain good tradeoff between BER and complexity for 400 Gb E electrical link.展开更多
Underwater acoustic channels pose a great difficulty for the development of high speed communication due to highly limited band-width as well as hostile multipath interference. Enlightened by rapid progress of multipl...Underwater acoustic channels pose a great difficulty for the development of high speed communication due to highly limited band-width as well as hostile multipath interference. Enlightened by rapid progress of multiple-input multiple-output (MIMO) technologies in wireless communication scenarios, MIMO systems offer a potential solution by enabling multiple spatially parallel communication channels to improve communication performance as well as capacity. For MIMO acoustic communications, deep sea channels offer substantial spatial diversity among multiple channels that can be exploited to address simultaneous multipath and co-channel interference. At the same time, there are increasing requirements for high speed underwater communication in very shallow water area (for example, a depth less than 10 m). In this paper, a space-time multichannel adaptive receiver consisting of multiple decision feedback equalizers (DFE) is adopted as the receiver for a very shallow water MIMO acoustic communication system. The performance of multichannel DFE receivers with relatively small number of receiving elements are analyzed and compared with that of the multichannel time reversal receiver to evaluate the impact of limited spatial diversity on multi-channel equalization and time reversal processing. The results of sea trials in a very shallow water channel are presented to demonstrate the feasibility of very shallow water MIMO acoustic communication.展开更多
This paper presents a lOGb/s highspeed equalizer as the frontend of a receiver for backplane communication. The equalizer combines an analog equalizer and a twotap decisionfeedback equal izer in a halfrate structure t...This paper presents a lOGb/s highspeed equalizer as the frontend of a receiver for backplane communication. The equalizer combines an analog equalizer and a twotap decisionfeedback equal izer in a halfrate structure to reduce the intersymbolinterference (ISI) of the communication chan nel. By employing inductive peaking technique for the highfrequency boost circuit, the bandwidth and the boost of the analog equalizer are improved. The decisionfeedback equalizer optimizes the size of the CMLbased circuit such as D flipflops (DFF) and multiplex (MUX), shortening the feedback path delay and speeding up the operation considerably. Designed in the 0. 181μm CMOS technology, the equalizer delivers 10Gb/s data over 18in FR4 trace with 28dB loss while drawing 27mW from a 1.8V supply. The overall chip area including pads is 0. 6 -0.7mm2.展开更多
A decoding method complemented by Maximum Likelihood (ML) detection for V-BLAST (Verti- cal Bell Labs Layered Space-Time) system is presented. The ranked layers are divided into several groups. ML decoding is performe...A decoding method complemented by Maximum Likelihood (ML) detection for V-BLAST (Verti- cal Bell Labs Layered Space-Time) system is presented. The ranked layers are divided into several groups. ML decoding is performed jointly for the layers within the same group while the Decision Feedback Equalization (DFE) is performed for groups. Based on the assumption of QPSK modulation and the quasi-static flat fading channel, simulations are made to testify the performance of the proposed algorithm. The results show that the algorithm outperforms the original V-BLAST detection dramatically in Symbol Error Probability (SEP) per- formance. Specifically, Signal-to-Noise Ratio (SNR) improvement of 3.4dB is obtained for SEP of 10?2 (4×4 case), with a reasonable complexity maintained.展开更多
This paper presents a 0.18μm CMOS 6.25 Gb/s equalizer for high speed backplane communication. The proposed equalizer is a combined one consisting of a one-tap feed-forward equalizer (FFE) and a two-tap half-rate de...This paper presents a 0.18μm CMOS 6.25 Gb/s equalizer for high speed backplane communication. The proposed equalizer is a combined one consisting of a one-tap feed-forward equalizer (FFE) and a two-tap half-rate decision feedback equalizer (DFE) in order to cancel both pre-cursor and post-cursor ISI. By employing an active-inductive peaking circuit for the delay line, the bandwidth of the FFE is increased and the area cost is minimized. CML-based circuits such as DFFs, summers and multiplexes all help to improve the speed of DFEs. Measurement results illustrate that the equalizer operates well when equalizing 6.25 Gb/s data is passed over a 30-inch channel with a loss of 22 dB and consumes 55.8 mW with the supply voltage of 1.8 V. The overall chip area including pads is 0.3 × 0.5 mm^2.展开更多
We propose an efficient low bit error rate(BER) and low complexity multiple-input multiple-output(MIMO) multiuser detection(MUD) method for use with multiuser MIMO orthogonal frequency division multiplexing(OFDM) syst...We propose an efficient low bit error rate(BER) and low complexity multiple-input multiple-output(MIMO) multiuser detection(MUD) method for use with multiuser MIMO orthogonal frequency division multiplexing(OFDM) systems.It is a hybrid method combining a multiuser-interference-cancellation-based decision feedback equalizer using error feedback filter(MIMO MIC DFE-EFF) and a differential algorithm.The proposed method,termed 'MIMO MIC DFE-EFF with a differential algorithm' for short,has a multiuser feedback structure.We describe the schemes of MIMO MIC DFE-EFF and MIMO MIC DFE-EFF with a differential algorithm,and compare their minimum mean square error(MMSE) performance and computational complexity.Simulation results show that a significant performance gain can be achieved by employing the MIMO MIC DFE-EFF detection algorithm in the context of a multiuser MIMO-OFDM system over frequency selective Rayleigh channel.MIMO MIC DFE-EFF with the differential algorithm improves both computational efficiency and BER performance in a multistage structure relative to conventional DFE-EFF,though there is a small reduction in system performance compared with MIMO MIC DFE-EFF without the differential algorithm.展开更多
文摘MIMO-DFE(Multiple-Input-Multiple-Output Decision Feedback Equalizer) based receiver architectures are researched recently to detect signals in BLAST(Bell laboratories LAyered Space-Time) over frequency-selective channels. Due to their recursive structure, these receivers may suffer from error propagation which results in an overall mean square error degradation. An MIMO-DFE based BLAST receiver with limited error propagation to combat frequencyselective channel is proposed, which employs both norm constraint on feedback filter taps and soft decision device. Simulation results show that the proposed receiver outperforms conventional ones in various frequency selective channels.
基金Supported by the High Technology Research and Development Programme of China (No. 2003AA31g030).
文摘A 6.25 Gbps SerDes core used in the high signed based on the OIF-CEI-02.0 standard. To speed backplane communication receiver has been decounteract the serious Inter-Syrmbol-Interference (ISI), the core employed a half-rate four-tap decision feedback equalizer (DFE). The equalizer used the Signsign least mean-squared (SS-LMS) algorithm to realize the coefficient adaptation. An automatic gain control (AGC) amplifier with the sign least mean-squared (S-LMS) algorithm has been used to compensate the transmission media loss. To recover the clock signal from the input data serial and provide for the DFE and AGC, a bang-bang clock recovery (BB-CR) is adopted. A third order phase loop loek (PLL) model was proposed to predict characteristics of the BB-CR. The core has been verified by behavioral modeling in MATLAB. The results indicate that the core can meet the specifications of the backplane receiver. The DFE recovered data over a 34" FR-4 backplane has a peak-to-peak jitter of 17 ps, a horizontal eye opening of 0.87 UI, and a vertical eye opening of 500 mVpp.
基金Supported by the National Natural Science Foundation of China(No.61471119)
文摘This paper evaluates the effect of decision feedback equalizer( DFE) error propagation for400 Gb/s Ethernet( 400 GbE) electrical link in order to propose some effective methods to improve bit error rate( BER). First,an analytical model for DFE burst error length distribution is proposed and simulated based on a NRZ electrical link in which a 5-tap DFE combined with a multiple-tap feed forward equalizer( FFE) is included. Then,a detailed derivation for BER considering DFE error propagation is given based on the distribution of burst error run length and the BER performance with and without forward error correction( FEC) is simulated too. After that,this paper investigates several MUX-based FEC interleaving methods including their complexity and latency in order to improve BER further. At last,three FEC interleaving schemes are compared not only in interleaving gain,but also in hardware complexities and latencies. Simulation results show that pre-interleave bit muxing can obtain good tradeoff between BER and complexity for 400 Gb E electrical link.
基金Supported by the National Natural Science Foundation of China (Nos. 11274259, 11574258) and the Open Project Program of the Key Laboratory of Underwater Acoustic Signal Processing, the Minister of Educat on (Southeast Un versity) (No. UASP1305).
文摘Underwater acoustic channels pose a great difficulty for the development of high speed communication due to highly limited band-width as well as hostile multipath interference. Enlightened by rapid progress of multiple-input multiple-output (MIMO) technologies in wireless communication scenarios, MIMO systems offer a potential solution by enabling multiple spatially parallel communication channels to improve communication performance as well as capacity. For MIMO acoustic communications, deep sea channels offer substantial spatial diversity among multiple channels that can be exploited to address simultaneous multipath and co-channel interference. At the same time, there are increasing requirements for high speed underwater communication in very shallow water area (for example, a depth less than 10 m). In this paper, a space-time multichannel adaptive receiver consisting of multiple decision feedback equalizers (DFE) is adopted as the receiver for a very shallow water MIMO acoustic communication system. The performance of multichannel DFE receivers with relatively small number of receiving elements are analyzed and compared with that of the multichannel time reversal receiver to evaluate the impact of limited spatial diversity on multi-channel equalization and time reversal processing. The results of sea trials in a very shallow water channel are presented to demonstrate the feasibility of very shallow water MIMO acoustic communication.
基金Supported by the National High Technology Research and Development Programme of China(No.2011AA10305)
文摘This paper presents a lOGb/s highspeed equalizer as the frontend of a receiver for backplane communication. The equalizer combines an analog equalizer and a twotap decisionfeedback equal izer in a halfrate structure to reduce the intersymbolinterference (ISI) of the communication chan nel. By employing inductive peaking technique for the highfrequency boost circuit, the bandwidth and the boost of the analog equalizer are improved. The decisionfeedback equalizer optimizes the size of the CMLbased circuit such as D flipflops (DFF) and multiplex (MUX), shortening the feedback path delay and speeding up the operation considerably. Designed in the 0. 181μm CMOS technology, the equalizer delivers 10Gb/s data over 18in FR4 trace with 28dB loss while drawing 27mW from a 1.8V supply. The overall chip area including pads is 0. 6 -0.7mm2.
基金Supported by the National Natural Science Foundation of China (No.60172029).
文摘A decoding method complemented by Maximum Likelihood (ML) detection for V-BLAST (Verti- cal Bell Labs Layered Space-Time) system is presented. The ranked layers are divided into several groups. ML decoding is performed jointly for the layers within the same group while the Decision Feedback Equalization (DFE) is performed for groups. Based on the assumption of QPSK modulation and the quasi-static flat fading channel, simulations are made to testify the performance of the proposed algorithm. The results show that the algorithm outperforms the original V-BLAST detection dramatically in Symbol Error Probability (SEP) per- formance. Specifically, Signal-to-Noise Ratio (SNR) improvement of 3.4dB is obtained for SEP of 10?2 (4×4 case), with a reasonable complexity maintained.
文摘This paper presents a 0.18μm CMOS 6.25 Gb/s equalizer for high speed backplane communication. The proposed equalizer is a combined one consisting of a one-tap feed-forward equalizer (FFE) and a two-tap half-rate decision feedback equalizer (DFE) in order to cancel both pre-cursor and post-cursor ISI. By employing an active-inductive peaking circuit for the delay line, the bandwidth of the FFE is increased and the area cost is minimized. CML-based circuits such as DFFs, summers and multiplexes all help to improve the speed of DFEs. Measurement results illustrate that the equalizer operates well when equalizing 6.25 Gb/s data is passed over a 30-inch channel with a loss of 22 dB and consumes 55.8 mW with the supply voltage of 1.8 V. The overall chip area including pads is 0.3 × 0.5 mm^2.
基金supported by the National Science and Technology Pillar Program (Nos 2008BAH30B12 and 2008BAH30B09)the Important National Science and Technology Specific Projects (Nos 2008ZX 03003-004, 2009ZX03003-008, 2009ZX03003-009, and 2009ZX 03002-009)+1 种基金the National Natural Science Foundation of China (No 60802009)the National High-Tech R & D Program (863) of China (Nos 2008AA01Z204 and 2009AA01Z205)
文摘We propose an efficient low bit error rate(BER) and low complexity multiple-input multiple-output(MIMO) multiuser detection(MUD) method for use with multiuser MIMO orthogonal frequency division multiplexing(OFDM) systems.It is a hybrid method combining a multiuser-interference-cancellation-based decision feedback equalizer using error feedback filter(MIMO MIC DFE-EFF) and a differential algorithm.The proposed method,termed 'MIMO MIC DFE-EFF with a differential algorithm' for short,has a multiuser feedback structure.We describe the schemes of MIMO MIC DFE-EFF and MIMO MIC DFE-EFF with a differential algorithm,and compare their minimum mean square error(MMSE) performance and computational complexity.Simulation results show that a significant performance gain can be achieved by employing the MIMO MIC DFE-EFF detection algorithm in the context of a multiuser MIMO-OFDM system over frequency selective Rayleigh channel.MIMO MIC DFE-EFF with the differential algorithm improves both computational efficiency and BER performance in a multistage structure relative to conventional DFE-EFF,though there is a small reduction in system performance compared with MIMO MIC DFE-EFF without the differential algorithm.