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DRS4在PET上的应用研究 被引量:2
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作者 杜成名 陈金达 +4 位作者 杨海波 成科 张秀玲 徐瑚珊 胡正国 《核电子学与探测技术》 CAS 北大核心 2015年第6期577-580,共4页
利用8+1通道DRS4采集板作为PMT的电子学读出和数据采集系统,由H8500耦合La Br3晶体阵列以及XP20D0耦合La Br3晶体条组合成的探测器对22Na 511 ke Vγ射线进行了测试。经波形数字化处理后,单个La Br3晶体条FWHM为3.42%,DRS4系统获得La Br... 利用8+1通道DRS4采集板作为PMT的电子学读出和数据采集系统,由H8500耦合La Br3晶体阵列以及XP20D0耦合La Br3晶体条组合成的探测器对22Na 511 ke Vγ射线进行了测试。经波形数字化处理后,单个La Br3晶体条FWHM为3.42%,DRS4系统获得La Br3晶体阵列位置映射图散点清晰,一维位置谱峰Sigma值小于CAMAC系统。实验表明:DRS4满足PET数据采集系统要求,可大幅消减电子学的规模和功耗,有利于PET系统的小型化和降低搭建成本。 展开更多
关键词 数字化波形分析法 drs4 溴化镧晶体 PET 能量分辨 位置分辨
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Design and offline processing of an ultrafast digitizer based on internal cascaded DRS4
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作者 Ya-Fei Du Jun Wu +4 位作者 Chen Yuan Bo Yang Cen-Ming Ye Chuan-Fei Zhang Yi-Nong Liu 《Nuclear Science and Techniques》 SCIE CAS CSCD 2019年第8期35-41,共7页
In this paper, we present an ultrafast digitizer utilizing the DRS4 switched capacitor array applicationspecific integrated circuit to achieve an ultrafast sampling speed of at most 5 GS/s. We cascaded all eight chann... In this paper, we present an ultrafast digitizer utilizing the DRS4 switched capacitor array applicationspecific integrated circuit to achieve an ultrafast sampling speed of at most 5 GS/s. We cascaded all eight channels(sub-channels) of a single DRS4 chip for increased storage depth. The digitizer contains four DRS4 chips, a quadchannel analog-to-digital converter,a controlling fieldprogrammable gate array, a PXI interface, and an SFP+connector. Consequently, each DRS4 channel has a depth of 8192 points and a vertical resolution of 14 bits. The readout sequences should be broken into several segments and then reordered to obtain the correct sequential data sets, and this offline procedure varies in different readout modes. This paper describes the design and implementation of the hardware;in particular, the respective processing procedures are described in detail. Furthermore, the offset error is calibrated and corrected to improve the precision of the captured waveform in both single-channel and highresolution modes. 展开更多
关键词 ULTRAFAST DIGITIZER drs4 CASCADE READOUT
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Three-detector setup for PAL spectrometer based on DRS4 waveform digitizing board
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作者 安然 陈祥磊 +9 位作者 代传波 郭晓彬 龚玉巍 李清华 任才 刘艳芬 郭俊清 丛龙翰 叶邦角 郭智荣 《Nuclear Science and Techniques》 SCIE CAS CSCD 2015年第4期57-60,共4页
A digital three-detector positron lifetime spectrometer was developed.It consists of a DRS4 waveform digitizing board and three La Br3scintillation detectors coupled to XP2020Q photomultiplier tubes.DRS4 waveform digi... A digital three-detector positron lifetime spectrometer was developed.It consists of a DRS4 waveform digitizing board and three La Br3scintillation detectors coupled to XP2020Q photomultiplier tubes.DRS4 waveform digitizing allows data sampling at up to 5 GSPS with high amplitude resolution,with good time scale linearity and stability.In the triple-coincidence,the new system could reach a 195 ps time resolution,which is better than the conventional analog apparatus with the same detectors.This spectrometer can be applied to the other scintillation timing measurements with picoseconds accuracy. 展开更多
关键词 闪烁探测器 波形数字化 数字化板 光谱仪 PAL 设置 正电子寿命 光电倍增管
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Application of the DRS4 chip for GHz waveform digitizing circuits 被引量:4
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作者 杨海波 苏弘 +4 位作者 孔洁 成科 陈金达 杜成明 张惊蛰 《Chinese Physics C》 SCIE CAS CSCD 2015年第5期73-79,共7页
A new fast waveform sampling digitizing circuit based on the domino ring sampler (DRS), a switched capacitor array (SCA) chip, is presented in this paper, which is different from the traditional waveform digitizin... A new fast waveform sampling digitizing circuit based on the domino ring sampler (DRS), a switched capacitor array (SCA) chip, is presented in this paper, which is different from the traditional waveform digitizing circuit constructed with an analog to digital converter (ADC) or time to digital converter. A DRS4 chip is used as a core device in our circuit, which has a fast sampling rate up to five gigabit samples per second (GSPS). Quite satisfactory results are acquired by the preliminary performance test for this circuit board. Eight channels can be provided by one board, which has a 1 V input dynamic range for each channel. The circuit linearity is better than 0.1%, the noise is less than 0.5 mV (root mean square, RMS), and its time resolution is about 50 ps. Several boards can be cascaded to construct a multi-board system. The advantages of high resolution, low cost, low power dissipation, high channel density and small size make the circuit board useful not only for physics experiments, but also for other applications. 展开更多
关键词 drs4 waveform sampling digitizing circuit high sampling rate high resolution
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A new positron annihilation lifetime spectrometer based on DRS4 waveform digitizing board
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作者 安然 成斌 +3 位作者 刘艳芬 叶邦角 孔伟 Stefan Ritt 《Chinese Physics C》 SCIE CAS CSCD 2014年第5期48-52,共5页
A new simple digital positron lifetime spectrometer has been developed. It includes a DRS4 waveform digitizing board and two scintillation detectors based on the XP2020Q photomultiplier tubes and LaBr3 scintillators. ... A new simple digital positron lifetime spectrometer has been developed. It includes a DRS4 waveform digitizing board and two scintillation detectors based on the XP2020Q photomultiplier tubes and LaBr3 scintillators. The DRS4 waveform digitizing can handle small pulses, down to few tens of millivolts, and its time scale linearity and stability are very good. The new system has reached a 206 ps time resolution, which is better than the conventional analog apparatus using the same detectors. These improvements make this spectrometer more simple and convenient in comparison with other spectrometers, and it can be applied to the other scintillation timing measurements with picosecond accuracy. 展开更多
关键词 digital lifetime spectrometer TIMING waveform sampling drs4 chip
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FPGA-based α/γ pulse shape discrimination for BaF_2 detector using 2-GSPS fast waveform sampling 被引量:3
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作者 Chen-Fei Yang Chang-Qing Feng +1 位作者 Shu-Bin Liu Qi An 《Nuclear Science and Techniques》 SCIE CAS CSCD 2017年第2期24-29,共6页
Four FPGA-based α/γ pulse shape discrimination algorithms for Ba F2 detector are investigated and compared in this paper. A 2-GSPS fast waveform sampling board based on DRS4 chip is employed to sample the pulses. Th... Four FPGA-based α/γ pulse shape discrimination algorithms for Ba F2 detector are investigated and compared in this paper. A 2-GSPS fast waveform sampling board based on DRS4 chip is employed to sample the pulses. The test results with a22 Na γ-source and the natural radioactivity of Ba F2 show good discrimination performance of the algorithms, with false rates around 1%. Small logical resource occupancy and short dead time are achieved. About 4400 slices are used in FPGA for pulse sampling and real-time discrimination altogether. 展开更多
关键词 BaF2 PULSE extraction a/c DISCRIMINATION drs4 FPGA
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基于SCA技术的高速数据采集电路研究
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作者 廖顺 杨海波 +4 位作者 张洪辉 周显才 张洪林 闫江 赵承心 《原子核物理评论》 CAS CSCD 北大核心 2023年第2期237-243,共7页
基于开关电容矩阵(Switched Capacitor Array,SCA)的波形数字化技术是未来物理实验装置前端读出电子学的重要发展方向之一。本工作设计了一种基于SCA芯片DRS4(Domino Ring Sampler 4)的超高速波形数字化数据采集电路。DRS4单通道可以最... 基于开关电容矩阵(Switched Capacitor Array,SCA)的波形数字化技术是未来物理实验装置前端读出电子学的重要发展方向之一。本工作设计了一种基于SCA芯片DRS4(Domino Ring Sampler 4)的超高速波形数字化数据采集电路。DRS4单通道可以最高以5 GHz的采样率对探测器输出信号进行全波形采样。该电路主要由模拟调理电路、DRS4电路、ADC(Analog-to-Digital Converter)电路、FPGA(Field-Programmable Gate Array)、DAC(Digital-to-Analog Converter)电路、触发电路和接口电路等组成。性能测试表明,该电路通道的噪声小于0.5 mV,积分非线性(Integral Non-Linearity,INL)优于1%。本电路模拟输入带宽高,采样率700MHz~5 GHz可调,具有良好的非线性。该数据采集电路具有一定的通用性,适用于多种类型的物理实验装置中的探测器读出。 展开更多
关键词 开关电容阵列 drs4 波形采样 性能测试
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Design of a high-sampling-rate electronic module for array-detector positron annihilation lifetime measurements
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作者 Jiale Cai Daowu Li +7 位作者 Yingjie Wang Zhiming Zhang Peilin Wang Haohui Tang Baoyi Wang Xingzhong Cao Fuyan Liu Long Wei 《Radiation Detection Technology and Methods》 CSCD 2019年第3期127-135,共9页
Introduction In this study,a high-time-resolution electronic module with a high channel density and low power consumption was designed for the measurement of the multi-detector array positron annihilation lifetimes.Th... Introduction In this study,a high-time-resolution electronic module with a high channel density and low power consumption was designed for the measurement of the multi-detector array positron annihilation lifetimes.This electronic module consisted of 32 input channels,and each channel provided a high sampling rate up to 5.12 GSPS based on a Domino Ring Sampler 4(DRS4)chip.Compared to the high-speed flash analog-digital converter(FADC),DRS4 chip has a higher channel density with an affordable lower price and power consumption.Methods The developed electronic module was also capable of real-time data analysis for directly extracting the time information of input signals at the data acquisition site,thereby significantly decreasing the data rate.The digital constant fraction discriminator(DCFD)algorithm was implemented in the field programmable gate array(FPGA)for performing the time pick-up.Results The coincidence time resolution of the electronic module was measured,and the test results revealed a value of 26 ps.A prototypical 16-pixel detector module of the multi-detector system was evaluated using this electronic module,and the coincidence time resolution of the prototypical module was 411.84 ps.Conclusions The electronic module was confirmed to satisfy the severe requirements of the multi-array-detector positron annihilation lifetime measurement system.It was also suitable for other high-time-resolution,high-channel-density,costeffective,and low-power-consumption applications. 展开更多
关键词 Digital constant fraction discriminator FPGA drs4 Positron lifetime
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