文章基于锂离子全电池及半电池体系,研究其在10%~90%荷电状态(state of charge,SOC)内直流阻抗(direct current resistance,DCR)与交流阻抗(electrochemical impedance spectroscopy,EIS)之间的关联性。结果表明:在一定脉冲电流范围内,...文章基于锂离子全电池及半电池体系,研究其在10%~90%荷电状态(state of charge,SOC)内直流阻抗(direct current resistance,DCR)与交流阻抗(electrochemical impedance spectroscopy,EIS)之间的关联性。结果表明:在一定脉冲电流范围内,DCR的大小仅与脉冲时间有关;在1~100 mV的扰动电压范围内,EIS保持不变。当选取EIS谱图中交流阻抗处的时间常数t(Rs+Rf+Rct)作为DCR测试的脉冲时间时,对于全电池体系,2种阻抗测试方法在所考察的SOC范围内均具有较好的关联性,测得的阻抗值相对偏差小于14.2%;对于半电池体系,2种阻抗测试方法仅在40%~90%SOC内具有较好的关联性,得到的阻抗值相对偏差小于10.7%。该文将锂离子电池2种阻抗测试方法相关联,对锂离子电池阻抗的测试及分析具有一定的意义。展开更多
The influence of the virtual guard ring width(GRW)on the performance of the p-well/deep n-well single-photon avalanche diode(SPAD)in a 180 nm standard CMOS process was investigated.TCAD simulation demonstrates that th...The influence of the virtual guard ring width(GRW)on the performance of the p-well/deep n-well single-photon avalanche diode(SPAD)in a 180 nm standard CMOS process was investigated.TCAD simulation demonstrates that the electric field strength and current density in the guard ring are obviously enhanced when GRW is decreased to 1μm.It is experimentally found that,compared with an SPAD with GRW=2μm,the dark count rate(DCR)and afterpulsing probability(AP)of the SPAD with GRW=1μm is significantly increased by 2.7 times and twofold,respectively,meanwhile,its photon detection probability(PDP)is saturated and hard to be promoted at over 2 V excess bias voltage.Although the fill factor(FF)can be enlarged by reducing GRW,the dark noise of devices is negatively affected due to the enhanced trap-assisted tunneling(TAT)effect in the 1μm guard ring region.By comparison,the SPAD with GRW=2μm can achieve a better trade-off between the FF and noise performance.Our study provides a design guideline for guard rings to realize a low-noise SPAD for large-array applications.展开更多
文摘文章基于锂离子全电池及半电池体系,研究其在10%~90%荷电状态(state of charge,SOC)内直流阻抗(direct current resistance,DCR)与交流阻抗(electrochemical impedance spectroscopy,EIS)之间的关联性。结果表明:在一定脉冲电流范围内,DCR的大小仅与脉冲时间有关;在1~100 mV的扰动电压范围内,EIS保持不变。当选取EIS谱图中交流阻抗处的时间常数t(Rs+Rf+Rct)作为DCR测试的脉冲时间时,对于全电池体系,2种阻抗测试方法在所考察的SOC范围内均具有较好的关联性,测得的阻抗值相对偏差小于14.2%;对于半电池体系,2种阻抗测试方法仅在40%~90%SOC内具有较好的关联性,得到的阻抗值相对偏差小于10.7%。该文将锂离子电池2种阻抗测试方法相关联,对锂离子电池阻抗的测试及分析具有一定的意义。
基金supported by the Jiangsu Agricultural Science and Technology Innovation Fund of China(No.CX(21)3062)the National Natural Science Foundation of China(No.62171233).
文摘The influence of the virtual guard ring width(GRW)on the performance of the p-well/deep n-well single-photon avalanche diode(SPAD)in a 180 nm standard CMOS process was investigated.TCAD simulation demonstrates that the electric field strength and current density in the guard ring are obviously enhanced when GRW is decreased to 1μm.It is experimentally found that,compared with an SPAD with GRW=2μm,the dark count rate(DCR)and afterpulsing probability(AP)of the SPAD with GRW=1μm is significantly increased by 2.7 times and twofold,respectively,meanwhile,its photon detection probability(PDP)is saturated and hard to be promoted at over 2 V excess bias voltage.Although the fill factor(FF)can be enlarged by reducing GRW,the dark noise of devices is negatively affected due to the enhanced trap-assisted tunneling(TAT)effect in the 1μm guard ring region.By comparison,the SPAD with GRW=2μm can achieve a better trade-off between the FF and noise performance.Our study provides a design guideline for guard rings to realize a low-noise SPAD for large-array applications.
