EFFICIENT IMPLEMENTATION OF 3D FILTER FOR MOVING OBJECT EXTRACTION

In this paper the design and implementation of Multi-Dimensional (MD) filter, particularly 3-Dimensional (3D) filter, are presented. Digital (discrete domain) filters applied to image and video signal processing using the novel 3D multirate algorithms for efficient implementation of moving object extraction are engineered with an example. The multirate (decimation and/or interpolation) signal processing algorithms can achieve significant savings in computation and memory usage. The proposed algorithm uses the mapping relations of z-transfer functions between non-multirate and multirate mathematical expressions in terms of time-varying coefficient instead of traditional polyphase de- composition counterparts. The mapping properties can be readily used to efficiently analyze and synthesize MD multirate filters.

A 16 bit Stereo Audio ΣΔ A/D Converter

A 16 bit stereo audio novel stability fifth-order ∑△ A/D converter that consists of switched capacitor ∑△ modulators, a decimation filter, and a bandgap circuit is proposed. A method for the stabilization of a high order single stage ∑△ modulator is also proposed. A new multistage comb filter is used for the front end decimation filter. The ∑△ A/D converter achieves a peak SNR of 96dB and a dynamic range of 96dB. The ADC was implemented in 0. 5μm 5V CMOS technology. The chip die area occupies only 4. 1mm × 2.4mm and dissipates 90mW.

2-D MULTIRATE ALGORITHMS FOR EFFICIENT IMPLEMENTATION OF EDGE DETECTION

Edge detection is a fundamental issue in image analysis. This paper proposes multirate algorithms for efficient implementation of edge detector, and a design example is illustrated.The multirate (decimation and/or interpolation) signal processing algorithms can achieve considerable savings in computation and storage. The proposed algorithms result in mapping relations of their z-transfer functions between non-multirate and multirate mathematical expressions in terms of time-varying coefficient instead of traditional polyphase decomposition counterparts.The mapping properties can be readily utilized to efficiently analyze and synthesize multirate edge detection filters. The Very high-speed Hardware Description Language (VHDL) simulation results verify efficiency of the algorithms for real-time Field Programmable Gate-Array (FPGA)implementation.

A high-performance,low-power ∑△ ADC for digital audio applications

A high-performance low-powerΣΔanalog-to-digital converter（ADC） for digital audio applications is described.It consists of a 2-1 cascadedΣΔmodulator and a decimation filter.Various design optimizations are implemented in the system design,circuit implementation and layout design,including a high-overload-level coefficient-optimized modulator architecture,a power-efficient class A/AB operational transconductance amplifier,as well as a multi-stage decimation filter conserving area and power consumption.The ADC is implemented in the SMIC 0.18-μm CMOS mixed-signal process.The experimental chip achieves a peak signal-to-noise-plus-distortion ratio of 90 dB and a dynamic range of 94 dB over 22.05-kHz audio band and occupies 2.1 mm^2,which dissipates only 2.1 mA quiescent current in the analog circuits.

A single die 1.2 V 55 to 95 dB DR delta sigma ADC with configurable modulator and OSR

A single die 1.2 V multi-stage noise shaping（Mash） 2-2 delta sigma analog to digital converter（ADC）for wide applications is implemented. The configurable Mash 2-2 modulator with a new decimation filter design is presented to achieve wide and high dynamic range（DR） for multiple practical applications. The novel modulator can be configured as a Mash 2-2 modulator for high precision or a 2-order modulator for low DR. The decimation filter is designed to select the OSR flexibly among cascaded integrator comb（CIC） filter and two half-band filters（HBF）. The serial peripheral interface（SPI） can be used to adjust the sampling frequency and the oversampling ratio（OSR）. The design was fabricated in a 0.13 m CMOS process with an area of 0.91 mm2and a total power of 5.2 mW. The measurement results show that the dynamic range（DR） of the proposed ADC can change from 55to 95 dB with the configurable OSR from 16 to 256. The spurious free dynamic range（SFDR） and signal-to-noise distortion ratio（SNDR） can get 99 dB and 86.5 dB, respectively.