We propose a trellis-compressed maximum likelihood sequence estimation(TC-MLSE)-assisted sliding-block decision feedback equalizer(DFE)to suppress the error propagation resulting from the DFE in high-speed systems.We ...We propose a trellis-compressed maximum likelihood sequence estimation(TC-MLSE)-assisted sliding-block decision feedback equalizer(DFE)to suppress the error propagation resulting from the DFE in high-speed systems.We use an out-ofrange detector to detect the end of burst errors from the DFE and activate the optional TC-MLSE to correct burst errors.We conduct experiments to transmit a 201-Gbit/s PAM-8 signal.The results show that the proposed method achieves a bit error rate of 3.65×10^(-3),which is close to that of MLSE.The optional MLSE is only activated when needed and processes 11.4%of the total symbols.Moreover,the proposed method compresses the maximum length of burst errors from 19 to 5.展开更多
A novel approach to survivor memory unit of Decision Feedback Sequence Estimator(DFSE) for 1000BASE-T transceiver based on hybrid architecture of the classical register-exchange and trace-back methods is proposed.The ...A novel approach to survivor memory unit of Decision Feedback Sequence Estimator(DFSE) for 1000BASE-T transceiver based on hybrid architecture of the classical register-exchange and trace-back methods is proposed.The proposed architecture is investigated with special emphasis on low power and small decoder latency,in which a dedicated register-exchange module is designed to provide tentative survivor symbols with zero latency,and a high-speed trace back logic is presented to meet the tight latency budget specified for 1000BASE-T transceiver.Furthermore,clock-gating register banks are constructed for power saving.VLSI implementation reveals that,the proposed architecture provides about 40% savings in power consumption compared to the traditional register-exchange architecture.展开更多
Types of hybrid architectures survivor memory unit (SMU) is presented,which are applicable to IEEE 802.3 ab 1000 Base-T Gigabit Ethernet (GbE) transceiver. Area, power and decoder latency were taken into account and m...Types of hybrid architectures survivor memory unit (SMU) is presented,which are applicable to IEEE 802.3 ab 1000 Base-T Gigabit Ethernet (GbE) transceiver. Area, power and decoder latency were taken into account and most efficient architectures were compared to optimize area/power tradeoff in different kinds of applications. Suitable SMU architectures are given out respectively in area-restrict, power-restrict and latency-restrict designs. A power-efficient architecture was selected in our GbE project. It provides 48% improvement in area and 71% amelioration in power, compared to classical register exchange architecture (REA) SMU.展开更多
基金This work was supported by the National Natural Science Foundation of China(NSFC)(Nos.62301128,61871082,and 62111530150)the Open Fund of IPOC(BUPT)(No.IPOC2020A011)+1 种基金the STCSM(No.SKLSFO2021-01)the Fundamental Research Funds for the Central Universities(Nos.ZYGX2020ZB043 and ZYGX2019J008).
文摘We propose a trellis-compressed maximum likelihood sequence estimation(TC-MLSE)-assisted sliding-block decision feedback equalizer(DFE)to suppress the error propagation resulting from the DFE in high-speed systems.We use an out-ofrange detector to detect the end of burst errors from the DFE and activate the optional TC-MLSE to correct burst errors.We conduct experiments to transmit a 201-Gbit/s PAM-8 signal.The results show that the proposed method achieves a bit error rate of 3.65×10^(-3),which is close to that of MLSE.The optional MLSE is only activated when needed and processes 11.4%of the total symbols.Moreover,the proposed method compresses the maximum length of burst errors from 19 to 5.
文摘A novel approach to survivor memory unit of Decision Feedback Sequence Estimator(DFSE) for 1000BASE-T transceiver based on hybrid architecture of the classical register-exchange and trace-back methods is proposed.The proposed architecture is investigated with special emphasis on low power and small decoder latency,in which a dedicated register-exchange module is designed to provide tentative survivor symbols with zero latency,and a high-speed trace back logic is presented to meet the tight latency budget specified for 1000BASE-T transceiver.Furthermore,clock-gating register banks are constructed for power saving.VLSI implementation reveals that,the proposed architecture provides about 40% savings in power consumption compared to the traditional register-exchange architecture.
基金National Science Fund for Creative ResearchGroups (No.60521002)Shanghai NaturalScience Foundation(No.037062022)
文摘Types of hybrid architectures survivor memory unit (SMU) is presented,which are applicable to IEEE 802.3 ab 1000 Base-T Gigabit Ethernet (GbE) transceiver. Area, power and decoder latency were taken into account and most efficient architectures were compared to optimize area/power tradeoff in different kinds of applications. Suitable SMU architectures are given out respectively in area-restrict, power-restrict and latency-restrict designs. A power-efficient architecture was selected in our GbE project. It provides 48% improvement in area and 71% amelioration in power, compared to classical register exchange architecture (REA) SMU.
