Oversampling sigma–delta(Σ–Δ)analog-to-digital converters(ADCs)are currently one of the most widely used architectures for high-resolution ADCs.The rapid development of integrated circuit manufacturing processes h...Oversampling sigma–delta(Σ–Δ)analog-to-digital converters(ADCs)are currently one of the most widely used architectures for high-resolution ADCs.The rapid development of integrated circuit manufacturing processes has allowed the realization of a high resolution in exchange for speed.Structurally,theΣ–ΔADC is divided into two parts:a front-end analog modulator and a back-end digital filter.The performance of the front-end analog modulator has a marked influence on the entireΣ–ΔADC system.In this paper,a 4-order single-loop switched-capacitor modulator with a CIFB(cascade-of-integrators feed-back)structure is proposed.Based on the chosen modulator architecture,the ASIC circuit is implemented using a chartered 0.35μm CMOS process with a chip area of 1.72×0.75 mm^2.The chip operates with a 3.3-V power supply and a power dissipation of 22 mW.According to the results,the performance of the designed modulator has been improved compared with a mature industrial chip and the effective number of bits(ENOB)was almost 18-bit.展开更多
This paper presents the design and experimental results of a continuous-time (CT) sigma-delta (ΣΔ) modulator with data-weighted average (DWA) technology for WiMAX applications. The proposed modulator comprises a thi...This paper presents the design and experimental results of a continuous-time (CT) sigma-delta (ΣΔ) modulator with data-weighted average (DWA) technology for WiMAX applications. The proposed modulator comprises a third-order active RC loop filter, internal quantizer operating at 160 MHz and three DAC circuits. A multi-bit quantizer is used to increase resolution and multi-bit non-return-to-zero (NRZ) DACs are adopted to reduce clock jitter sensitivity. The NRZ DAC circuits with quantizer excess loop delay compensation are set to be half the sampling period of the quantizer for increasing modulator stability. A dynamic element matching (DEM) technique is applied to multi-bit ΣΔ modulators to improve the nonlinearity of the internal DAC. This approach translates the harmonic distortion components of a nonideal DAC in the feedback loop of a ΣΔ modulator to high-frequency components. Capacitor tuning is utilized to overcome loop coefficient shifts due to process variations. The DWA technique is used for reducing DAC noise due to component mismatches. The prototype is implemented in TSMC 0.18 um CMOS process. Experimental results show that the ΣΔ modulator achieves 54-dB dynamic range, 51-dB SNR, and 48-dB SNDR over a 10-MHz signal bandwidth with an oversampling ratio (OSR) of 8, while dissipating 19.8 mW from a 1.2-V supply. Including pads, the chip area is 1.156 mm2.展开更多
Time-interleaved structure can promote the equivalent processing speed of a digital signal processing system. An improved time-interleaved error feedback delta sigma modulator( TI-EF-DSM)for digital transmitter applic...Time-interleaved structure can promote the equivalent processing speed of a digital signal processing system. An improved time-interleaved error feedback delta sigma modulator( TI-EF-DSM)for digital transmitter application is presented in this paper. Two TI-EF-DSMs are compared,one is a conventional directly implemented and the other is the improved. The processing speed of the proposed two-channel improved time-interleaved error feedback delta sigma modulator( ITI-EF-DSM) is higher than the conventional directly implemented TI-EF-DSM for shortened critical path. A digital transmitter based on the ITI-EF-DSM is implemented on field progrmmable gate array( FPGA). The long term evolution( LTE) signals with different bandwidths of 5 MHz,10 MHz and 20 MHz are used as the signal source to evaluate the transmitter. The achieved SNR is 41 dB for the 20 MHz LTE signal with the processing clock of only 184 MHz.展开更多
In this paper,in order to reduce power consumption and chip area,as well as to improve the performance of the bandpass sigma-delta modulator,a novel full differential feedforward fourth-order bandpass sigma-delta modu...In this paper,in order to reduce power consumption and chip area,as well as to improve the performance of the bandpass sigma-delta modulator,a novel full differential feedforward fourth-order bandpass sigma-delta modulator was proposed. It used a resonator based on Salo architecture,which employed doublesampling and double-delay technique. The results show that the proposed modulator can achieve lower power consumption and a lower capacitive load than the conventional bandpass modulators on the platform of Simulink. The circuit is implemented with TSMC0. 18 μm CMOS process and operates at a sampling frequency of 20 MHz, 80 MHz effective sampling frequency. Furthermore,it consumes 21. 2 mW from a 1. 8 V supply. The simulated peak signal-to-noise ratio( SNR) is 85. 9 dB and the dynamic range( DR) is 91 dB with 200 kHz bandwidth.展开更多
A fractional frequency divider based on phase switching and negative feedback delta-sigma modulator(NF-DSM) is presented. The phase switching circuit, realized by switching 8 signals generated by a divider-by-4 circui...A fractional frequency divider based on phase switching and negative feedback delta-sigma modulator(NF-DSM) is presented. The phase switching circuit, realized by switching 8 signals generated by a divider-by-4 circuit, is adopted to reduce the frequency division step. The NF-DSM, which can obtain smooth output spectra, is proposed to generate the fractional part of the division ratio, moreover, the integer part of the division ratio is realized by a divider-by-2/3 circuit chain. Fabricated in TSMC 0.18 μm RF CMOS technology, the fractional frequency divider achieves a measured operation frequency from 0.5 GHz to 8 GHz. With a 1.8 V supply voltage, the maximum current consumption of the whole divider is 17.5 mA, and the chip area is 0.58 mm^2, including the pads.展开更多
This paper investigates the design of digital Sigma-Delta Modulator (SDM) for fractional-N frequency synthesizer. Characteristics of SDMs are compared through theory analysis and simulation. The curve of maximum-loop-...This paper investigates the design of digital Sigma-Delta Modulator (SDM) for fractional-N frequency synthesizer. Characteristics of SDMs are compared through theory analysis and simulation. The curve of maximum-loop-bandwidth vs. maximum-phase-noise is suggested to be a new criterion to the performance of SDM,which greatly helps designers to select an appropriate SDM structure to meet their real application requirements and to reduce the cost as low as possible. A low-spur 3-order Mul-tistage Noise Shaping (MASH)-1-1-1 SDM using three 2-bit first-order cascaded modulators is proposed,which balances the requirements of tone-free and maximum operation frequency.展开更多
A new digital transmitter based on delta sigma modulator( DSM) with bus-splitting is presented in this paper. The second order low pass error-feedback delta sigma modulator( EF-DSM) is focused. The signal to noise rat...A new digital transmitter based on delta sigma modulator( DSM) with bus-splitting is presented in this paper. The second order low pass error-feedback delta sigma modulator( EF-DSM) is focused. The signal to noise ratio( SNR) of the EF-DSM is derived for different bus-splitting bits.Following the EF-DSM,a multi-bit digital up mixer is used for carrier frequency transform. In order to validate the theory of bus-splitting,two types of transmitters are implemented on FPGA for comparison,in which one is with non-bus-splitting and the other is with bus-splitting. The FPGA implemented transmitter with bus-splitting promotes the maximum operation speed by 39%,and reduces hardware consumptions more than 16%. Both single tone and orthogonal frequency division multiplexing( OFDM) signal source are used to evaluate the proposed transmitter.展开更多
In this paper, new complex band pass filter architecture for continuous time complex band pass sigma delta modulator is presented. In continuation of paper the modulator is designed for GPS and Galileo receiver. This ...In this paper, new complex band pass filter architecture for continuous time complex band pass sigma delta modulator is presented. In continuation of paper the modulator is designed for GPS and Galileo receiver. This modulator was simulated in standard 0.18 μm CMOS TSMC technology and has bandwidth of 2MHz and 4MHz for GPS and Galileo centered in 4.092 MHz. The dynamic range (DR) is 56.5/49 dB (GPS/Galileo) at sampling rate of 125 MHz. The modulator has power consumption of 4.1 mw with 3 V supply voltage.展开更多
基金funded by the Major Emerging Industrial Projects of Anhuithe Postdoctoral Project from Hefei
文摘Oversampling sigma–delta(Σ–Δ)analog-to-digital converters(ADCs)are currently one of the most widely used architectures for high-resolution ADCs.The rapid development of integrated circuit manufacturing processes has allowed the realization of a high resolution in exchange for speed.Structurally,theΣ–ΔADC is divided into two parts:a front-end analog modulator and a back-end digital filter.The performance of the front-end analog modulator has a marked influence on the entireΣ–ΔADC system.In this paper,a 4-order single-loop switched-capacitor modulator with a CIFB(cascade-of-integrators feed-back)structure is proposed.Based on the chosen modulator architecture,the ASIC circuit is implemented using a chartered 0.35μm CMOS process with a chip area of 1.72×0.75 mm^2.The chip operates with a 3.3-V power supply and a power dissipation of 22 mW.According to the results,the performance of the designed modulator has been improved compared with a mature industrial chip and the effective number of bits(ENOB)was almost 18-bit.
文摘This paper presents the design and experimental results of a continuous-time (CT) sigma-delta (ΣΔ) modulator with data-weighted average (DWA) technology for WiMAX applications. The proposed modulator comprises a third-order active RC loop filter, internal quantizer operating at 160 MHz and three DAC circuits. A multi-bit quantizer is used to increase resolution and multi-bit non-return-to-zero (NRZ) DACs are adopted to reduce clock jitter sensitivity. The NRZ DAC circuits with quantizer excess loop delay compensation are set to be half the sampling period of the quantizer for increasing modulator stability. A dynamic element matching (DEM) technique is applied to multi-bit ΣΔ modulators to improve the nonlinearity of the internal DAC. This approach translates the harmonic distortion components of a nonideal DAC in the feedback loop of a ΣΔ modulator to high-frequency components. Capacitor tuning is utilized to overcome loop coefficient shifts due to process variations. The DWA technique is used for reducing DAC noise due to component mismatches. The prototype is implemented in TSMC 0.18 um CMOS process. Experimental results show that the ΣΔ modulator achieves 54-dB dynamic range, 51-dB SNR, and 48-dB SNDR over a 10-MHz signal bandwidth with an oversampling ratio (OSR) of 8, while dissipating 19.8 mW from a 1.2-V supply. Including pads, the chip area is 1.156 mm2.
基金Supported by the National Natural Science Foundation of China(No.61674037)the National Key Research and Development Program of China(No.2016YFC0800400)+2 种基金the Priority Academic Program Development of Jiangsu Higher Education Institutionsthe National Power Grid Corp Science and Technology Project(No.SGTYHT/16-JS-198)the State Grid Nanjing Power Supply Company Project(No.1701052)
文摘Time-interleaved structure can promote the equivalent processing speed of a digital signal processing system. An improved time-interleaved error feedback delta sigma modulator( TI-EF-DSM)for digital transmitter application is presented in this paper. Two TI-EF-DSMs are compared,one is a conventional directly implemented and the other is the improved. The processing speed of the proposed two-channel improved time-interleaved error feedback delta sigma modulator( ITI-EF-DSM) is higher than the conventional directly implemented TI-EF-DSM for shortened critical path. A digital transmitter based on the ITI-EF-DSM is implemented on field progrmmable gate array( FPGA). The long term evolution( LTE) signals with different bandwidths of 5 MHz,10 MHz and 20 MHz are used as the signal source to evaluate the transmitter. The achieved SNR is 41 dB for the 20 MHz LTE signal with the processing clock of only 184 MHz.
基金Sponsored by the National Basic Research Program of China(Grant No.2012CB934104)
文摘In this paper,in order to reduce power consumption and chip area,as well as to improve the performance of the bandpass sigma-delta modulator,a novel full differential feedforward fourth-order bandpass sigma-delta modulator was proposed. It used a resonator based on Salo architecture,which employed doublesampling and double-delay technique. The results show that the proposed modulator can achieve lower power consumption and a lower capacitive load than the conventional bandpass modulators on the platform of Simulink. The circuit is implemented with TSMC0. 18 μm CMOS process and operates at a sampling frequency of 20 MHz, 80 MHz effective sampling frequency. Furthermore,it consumes 21. 2 mW from a 1. 8 V supply. The simulated peak signal-to-noise ratio( SNR) is 85. 9 dB and the dynamic range( DR) is 91 dB with 200 kHz bandwidth.
基金Supported by the National Natural Science Foundation of China(No.61674037)National Key Research and Development Program of China(No.2016YFC0800400)the Priority Academic Program Development of Jiangsu Higher Education Institutions
文摘A fractional frequency divider based on phase switching and negative feedback delta-sigma modulator(NF-DSM) is presented. The phase switching circuit, realized by switching 8 signals generated by a divider-by-4 circuit, is adopted to reduce the frequency division step. The NF-DSM, which can obtain smooth output spectra, is proposed to generate the fractional part of the division ratio, moreover, the integer part of the division ratio is realized by a divider-by-2/3 circuit chain. Fabricated in TSMC 0.18 μm RF CMOS technology, the fractional frequency divider achieves a measured operation frequency from 0.5 GHz to 8 GHz. With a 1.8 V supply voltage, the maximum current consumption of the whole divider is 17.5 mA, and the chip area is 0.58 mm^2, including the pads.
基金the National Natural Science Foundation of China (No. 60025101, No.90207001, and No. 90307016).
文摘This paper investigates the design of digital Sigma-Delta Modulator (SDM) for fractional-N frequency synthesizer. Characteristics of SDMs are compared through theory analysis and simulation. The curve of maximum-loop-bandwidth vs. maximum-phase-noise is suggested to be a new criterion to the performance of SDM,which greatly helps designers to select an appropriate SDM structure to meet their real application requirements and to reduce the cost as low as possible. A low-spur 3-order Mul-tistage Noise Shaping (MASH)-1-1-1 SDM using three 2-bit first-order cascaded modulators is proposed,which balances the requirements of tone-free and maximum operation frequency.
基金Supported by the National Natural Science Foundation of China(No.61674037)National Key Research and Development Program of China(No.2016YFC0800400)+1 种基金the Priority Academic Program Development of Jiangsu Higher Education Institutionsthe National Power Grid Corp Science and Technology Project(No.SGTYHT/16-JS-198)
文摘A new digital transmitter based on delta sigma modulator( DSM) with bus-splitting is presented in this paper. The second order low pass error-feedback delta sigma modulator( EF-DSM) is focused. The signal to noise ratio( SNR) of the EF-DSM is derived for different bus-splitting bits.Following the EF-DSM,a multi-bit digital up mixer is used for carrier frequency transform. In order to validate the theory of bus-splitting,two types of transmitters are implemented on FPGA for comparison,in which one is with non-bus-splitting and the other is with bus-splitting. The FPGA implemented transmitter with bus-splitting promotes the maximum operation speed by 39%,and reduces hardware consumptions more than 16%. Both single tone and orthogonal frequency division multiplexing( OFDM) signal source are used to evaluate the proposed transmitter.
文摘In this paper, new complex band pass filter architecture for continuous time complex band pass sigma delta modulator is presented. In continuation of paper the modulator is designed for GPS and Galileo receiver. This modulator was simulated in standard 0.18 μm CMOS TSMC technology and has bandwidth of 2MHz and 4MHz for GPS and Galileo centered in 4.092 MHz. The dynamic range (DR) is 56.5/49 dB (GPS/Galileo) at sampling rate of 125 MHz. The modulator has power consumption of 4.1 mw with 3 V supply voltage.
