For the frequency range of I kHz-lOMHz, the interface state density of Ni contacts on p-GaN is studied using capacitance-voltage (C-V) and conductance-frequency-voltage (G-f-V) measurements at room temperature. To...For the frequency range of I kHz-lOMHz, the interface state density of Ni contacts on p-GaN is studied using capacitance-voltage (C-V) and conductance-frequency-voltage (G-f-V) measurements at room temperature. To obtain the real capacitance and interface state density of the Ni/p-GaN structures, the effects of the series resistance (Rs) on high-frequency (SMHz) capacitance values measured at a reverse and a forward bias are investigated. The mean interface state densities obtained from the CHF-CLF capacitance and the conductance method are 2 ×1012 e V-1 cm-2 and 0.94 × 1012 eV-1 cm-2, respectively. Furthermore, the interface state density derived from the conductance method is higher than that reported from the Ni/n-GaN in the literature, which is ascribed to a poor crystal quality and to a large defect density of the Mg-doped p-GaN.展开更多
In order to investigate the characteristics and mechanisms of subthreshold voltage hysteresis(ΔV_(th,sub)) of 4 H-SiC metal-oxide-semiconductor field-effect transistors(MOSFETs),4 H-SiC planar and trench MOSFETs and ...In order to investigate the characteristics and mechanisms of subthreshold voltage hysteresis(ΔV_(th,sub)) of 4 H-SiC metal-oxide-semiconductor field-effect transistors(MOSFETs),4 H-SiC planar and trench MOSFETs and corresponding P-type planar and trench metal-oxide-semiconductor(MOS) capacitors are fabricated and characterized.Compared with planar MOSFEF,the trench MOSFET shows hardly larger ΔV_(th,sub) in wide temperature range from 25 0 C to 300 0 C.When operating temperature range is from 25 ℃ to 300 ℃,the off-state negative V_(gs) of planar and trench MOSFETs should be safely above-4 V and-2 V,respectively,to alleviate the effect of ΔV_(th,sub) on the normal operation.With the help of P-type planar and trench MOS capacitors,it is confirmed that the obvious ΔV_(th,sub) of 4 H-SiC MOSFET originates from the high density of the hole interface traps between intrinsic Fermi energy level(E_(i)) and valence band(E_(v)).The maximumΔV_(th,sub) of trench MOSFET is about twelve times larger than that of planar MOSFET,owing to higher density of interface states(D_(it)) between E_(i) and E_(v).These research results will be very helpful for the application of 4 H-SiC MOSFET and the improvement of ΔV_(th,sub) of 4 H-SiC MOSFET,especially in 4 H-SiC trench MOSFET.展开更多
We investigate the effects of NO annealing and forming gas (FG) annealing on the electrical properties of a SiO2/SiC interface by low-temperature conductance measurements. With nitrogen passivation, the density of i...We investigate the effects of NO annealing and forming gas (FG) annealing on the electrical properties of a SiO2/SiC interface by low-temperature conductance measurements. With nitrogen passivation, the density of interface states (DIT) is significantly reduced in the entire energy range, and the shift of flatband voltage, AVFB, is effectively suppressed to less than 0.4 V. However, very fast states are observed after NO annealing and the response frequencies are higher than 1 MHz at room temperature. After additional FG annealing, the DIT and AVFB are further reduced. The values of the DIT decrease to less than 1011 cm-2 eV- 1 for the energy range of Ec - ET 〉/0.4 eV. It is suggested that the fast states in shallow energy levels originated from the N atoms accumulating at the interface by NO annealing. Though FG annealing has a limited effect on these shallow traps, hydrogen can terminate the residual Si and C dangling bonds corresponding to traps at deep energy levels and improve the interface quality further. It is indicated that NO annealing in conjunction with FG annealing will be a better post-oxidation process method for high performance SiC MOSFETs.展开更多
基金Supported by the Natural Science Foundation of Jiangxi Province under Grant No 20133ACB20005the Key Program of National Natural Science Foundation of China under Grant No 41330318+3 种基金the Key Program of Science and Technology Research of Ministry of Education under Grant No NRE1515the Foundation of Training Academic and Technical Leaders for Main Majors of Jiangxi Province under Grant No 20142BCB22006the Research Foundation of Education Bureau of Jiangxi Province under Grant No GJJ14501the Engineering Research Center of Nuclear Technology Application(East China Institute of Technology)Ministry of Education under Grant NoHJSJYB2016-1
文摘For the frequency range of I kHz-lOMHz, the interface state density of Ni contacts on p-GaN is studied using capacitance-voltage (C-V) and conductance-frequency-voltage (G-f-V) measurements at room temperature. To obtain the real capacitance and interface state density of the Ni/p-GaN structures, the effects of the series resistance (Rs) on high-frequency (SMHz) capacitance values measured at a reverse and a forward bias are investigated. The mean interface state densities obtained from the CHF-CLF capacitance and the conductance method are 2 ×1012 e V-1 cm-2 and 0.94 × 1012 eV-1 cm-2, respectively. Furthermore, the interface state density derived from the conductance method is higher than that reported from the Ni/n-GaN in the literature, which is ascribed to a poor crystal quality and to a large defect density of the Mg-doped p-GaN.
基金Project supported by the National Key Research and Development Program of China(Grant No.2017YFB0903203)the National Natural Science Foundation of China(Grant No.62004033)China Postdoctoral Science Foundation(Grant No.2020M683287)。
文摘In order to investigate the characteristics and mechanisms of subthreshold voltage hysteresis(ΔV_(th,sub)) of 4 H-SiC metal-oxide-semiconductor field-effect transistors(MOSFETs),4 H-SiC planar and trench MOSFETs and corresponding P-type planar and trench metal-oxide-semiconductor(MOS) capacitors are fabricated and characterized.Compared with planar MOSFEF,the trench MOSFET shows hardly larger ΔV_(th,sub) in wide temperature range from 25 0 C to 300 0 C.When operating temperature range is from 25 ℃ to 300 ℃,the off-state negative V_(gs) of planar and trench MOSFETs should be safely above-4 V and-2 V,respectively,to alleviate the effect of ΔV_(th,sub) on the normal operation.With the help of P-type planar and trench MOS capacitors,it is confirmed that the obvious ΔV_(th,sub) of 4 H-SiC MOSFET originates from the high density of the hole interface traps between intrinsic Fermi energy level(E_(i)) and valence band(E_(v)).The maximumΔV_(th,sub) of trench MOSFET is about twelve times larger than that of planar MOSFET,owing to higher density of interface states(D_(it)) between E_(i) and E_(v).These research results will be very helpful for the application of 4 H-SiC MOSFET and the improvement of ΔV_(th,sub) of 4 H-SiC MOSFET,especially in 4 H-SiC trench MOSFET.
基金supported by the National Natural Science Foundation of China(Nos.61106080,61275042)the National Science and Technology Major Project of the Ministry of Science and Technology of China(No.2013ZX02305)
文摘We investigate the effects of NO annealing and forming gas (FG) annealing on the electrical properties of a SiO2/SiC interface by low-temperature conductance measurements. With nitrogen passivation, the density of interface states (DIT) is significantly reduced in the entire energy range, and the shift of flatband voltage, AVFB, is effectively suppressed to less than 0.4 V. However, very fast states are observed after NO annealing and the response frequencies are higher than 1 MHz at room temperature. After additional FG annealing, the DIT and AVFB are further reduced. The values of the DIT decrease to less than 1011 cm-2 eV- 1 for the energy range of Ec - ET 〉/0.4 eV. It is suggested that the fast states in shallow energy levels originated from the N atoms accumulating at the interface by NO annealing. Though FG annealing has a limited effect on these shallow traps, hydrogen can terminate the residual Si and C dangling bonds corresponding to traps at deep energy levels and improve the interface quality further. It is indicated that NO annealing in conjunction with FG annealing will be a better post-oxidation process method for high performance SiC MOSFETs.