Design Scheme of New Type Shell Raising and Feeding System of Medium-large Caliber Naval Gun

The medium -large caliber naval gun is still playing an important role in modern war. The development of highly automatic Shell Raising and Feeding System (SRFS) in the world has been briefly outlined. Several typical SRFS of medium-large caliber naval guns have been analyzed. A re-design of the system is introduced, in which systematic design method has been used to demonstrate its feasibility. The design goal of the system is to realize rapid shell feeding, with application to many types of shells, quick change of shell types , accurate and reliable feeding operation, simple mechanical structure and easy realization of shell withdrawing.

Design of a Low Power DSP with Distributed and Early Clock Gating

A novel clock structure of a low-power 16-bit very large instruction word (VLIW) digital signal processor (DSP) was proposed. To improve deterministic clock gating and to solve the drawback of conventional clock gating circuit in high speed circuit, a distributed and early clock gating method was developed on its instruction fetch & decoder unit, its pipelined data-path unit and its super-Harvard memory interface unit. The core was implemented following the Synopsys back-end flow under TSMC (Taiwan Silicon manufacture corporation) 0.18-μm 1.8-V 1P6M process, with a core size of 2 mm×2 mm. Result shows that it can run under 200 MHz with a power performance around 0.3 mW/MIPS. Meanwhile, only 39.7% circuit is active simultaneously in average, compared to its non-gating counterparts.

DESIGN OF TWO-PHASE SINUSOIDAL POWER CLOCK AND CLOCKED TRANSMISSION GATE ADIABATIC LOGIC CIRCUIT

First the research is conducted on the design of the two-phase sinusoidal power clock generator in this paper. Then the design of the new adiabatic logic circuit adopting the two-phase sinusoidal power clocks--Clocked Transmission Gate Adiabatic Logic （CTGAL） circuit is presented. This circuit makes use of the clocked transmission gates to sample the input signals, then the output loads are charged and discharged in a fully adiabatic manner by using bootstrapped N-Channel Metal Oxide Semiconductor （NMOS） and Complementary Metal Oxide Semiconductor （CMOS） latch structure. Finally, with the parameters of Taiwan Semiconductor Manufacturing Company （TSMC） 0.25um CMOS device, the transient energy consumption of CTGAL, Bootstrap Charge-Recovery Logic （BCRL） and Pass-transistor Adiabatic Logic （PAL） including their clock generators is simulated. The simulation result indicates that CTGAL circuit has the characteristic of remarkably low energy consumption.

Design and Application of Dietary Formula for Muscovy Duck at Different Growth Stages

In this study,feed formulation software REFS3000 was applied to design dietary formula for black-feather Muscovy duck at different growth stages,which provided the basic information for dietary combination in further feeding experiment,aiming at improving the targeted feeding level of duck in China.

Design and Assembly of an Improvised Logic Gates Simulator

This study aimed at designing and assembling an improvised Logic Gates Simulator that can be utilized as an instructional device in basic digital electronics instruction at Caraga State University Cabadbaran Campus, Philippines. This instructional device is believed to enhance the teaching-learning process and would also help address the scarcity of instructional equipment in the school and in the country. Descriptive method of research was employed to come up with the design of the simulator based on the course content of basic digital electronics subject. Acceptability of the improvised simulator based on standards set in this study was?gathered from the experts as respondents using a self-made questionnaire. The data were treated using average weighted mean utilizing parametric scales with verbal descriptions. Findings revealed that the improvised logic gates simulator is highly acceptable in terms of its cost and availability of components,?design and construction,operations, and troubleshooting features. It is concluded that the improvised logic gates simulator is at par in terms of standards on instructional devices based on the evaluation results of experts and is therefore recommended to be used in basic digital electronics instruction. The simulator is an innovative answer and an alternate solution to the scarcity of instructional materials and devices at Caraga State University Cabadbaran Campus.

Improving landscape Characteristics in Port Said’s El Sallam Garden via Observational and Space Syntax Analysis

This paper provides a comprehensive examination of El Sallam Garden in Port Said City,concentrating on its landscape characteristics and potential for design enhancement.This study looks at how space syntax can be used to assess the impact of a tree planting design’s spatial configuration on an urban park’s visual fields.Trees play an important role in determining the spatial characteristics of an outdoor space.According to space syntax theory,an urban area is a collection of connected spaces that can be represented by a matrix of quantitative properties known as syntactic measures.Computer simulations can be used to measure the quantitative properties of these matrices.This study uses space syntax techniques to assess how tree configurations and garden area which can affect the social structures of small-scale gardens in Port Said.It also looks at how these techniques can be used to predict the social structures of four garden zones in El Sallam Garden.The study includes an observational and space syntax study through comparative analysis of four garden zones in El Sallam garden.The results of the study show that the area and planting configurations of the garden had a significant effect on the syntactic social and visual measures of the urban garden.The conclusions and recommendations can be a useful tool for landscape architects,urban planners,and legislators who want to enhance public areas and encourage social interaction in urban settings.

Design and Implementation of an Efficient Reversible Comparator Using TR Gate

Reversible logic is a new emerging technology with many promising applications in optical information processing, low power (Complementary Metal Oxide Semiconductor) CMOS design, (De Oxy RiboNucleic Acid) DNA computing, etc. In industrial automation, comparators play an important role in segregating faulty patterns from good ones. In previous works, these comparators have been implemented with more number of reversible gates and computational complexity. All these comparators use propagation technique to compare the data. This will reduce the efficiency of the comparators. To overcome the problem, this paper proposes an efficient comparator using (Thapliyal Ranganathan) TR gate utilizing full subtraction and half subtraction algorithm which will improve the computation efficiency. The comparator design using half subtraction algorithm shows an improvement in terms of quantum cost. The comparator design using full subtraction algorithm shows effectiveness in reducing number of reversible gates required and garbage output.

Structure Design Considerations of a Sub-50nm Self-Aligned Double-Gate MOSFET

A comprehensive way to design a sub 50nm SADG MOSFET with the ability of being fabricated by improved CMOS technique is described.Under this way,the gate length and thickness of Si island of DG device show many different scaling limits for various elements.Meanwhile,the spacer insulator shows a kind of width thickness on device drain current and circuit speed.A model about that effect is developed and offers design consideration for future.A new design of channel doping profile,called SCD,is also discussed here in detail.The DG device with SCD can achieve a good balance between the volume inversion operation mode and the control of V th .Finally,a guideline to make a SADG MOSFET is presented.

DEM analysis of the influence of stirrer design on die filling with forced powder feeding

Die filling is a critical stage during powder compaction,which can significantly affect the product quality and efficiency.In this paper,a forced feeder is introduced attempting to improve the filling performance of a lab-scale die filling system.The die filling process is analysed with a graphics processing units(GPU)enhanced discrete element method(DEM).Various stirrer designs are assessed for a wide range of process settings(i.e.,stirrer speed,filling speed)to explore their influence on the die filling performance of free-flowing powder.Numerical results show that die filing with the novel helical-ribbon(i.e.,type D)stirrer design exhibits the highest filling ratio,implying that it is the most robust stirrer design for the feeder configuration considered.Furthermore,die filling performance with the type D stirrer design is a function of the stirrer speed and the filling speed.A positive variation of filling ratio(ηf>0%)can be ensured over the whole range of filling speed by adjusting the stirrer speed(i.e.,increasing the stirrer speed).The approach used in this study can not only help understand how the stirrer design affects the die filling performance but also guide the optimization of feeder system and process settings.

System-on-Chip Design Using High-Level Synthesis Tools

This paper addresses the challenges of System-on-Chip designs using High-Level Synthesis (HLS). HLS tools convert algorithms designed in C into hardware modules. This approach is a practical choice for developing complex applications. Nevertheless, certain hardware considerations are required when writing C applications for HLS tools. Hence, in order to demonstrate the fundamental hardware design concepts, a case studyis presented. Fast Fourier Transform (FFT) implementation in ANSI C is examined in order to explore the important design issues such as concurrency, data recurrences and memory accesses that need to be resolved before generating the hardware using HLS tools. There are additional language constraints that need to be addressed including use of pointers, recursion and floating point types.

ARCHITECTURE MODEL AND RESOURCE GRAPH BUILDING ALGORITHM FOR DETAILED FPGA ARCHITECTURE DESIGN

This paper addresses the issue of designing the detailed architectures of Field-Programmable Gate Arrays(FPGAs), which has a great impact on the overall performances of an FPGA in practice. Firstly, a novel FPGA architecture description model is proposed based on an easy-to-use file format known as YAML. This format permits the description of any detailed architecture of hard blocks and channels. Then a general algorithm of building FPGA resource graph is presented. The proposed model is scalable and capable of dealing with detailed architecture design and can be used in FPGA architecture evaluation system which is developed to enable detailed architecture design. Experimental results show that a maximum of 16.36% reduction in total wirelength and a maximum of 9.34% reduction in router effort can be obtained by making very little changes to detailed architectures, which verifies the necessity and effectiveness of the proposed model.

Improving Bandwidth of Yagi-Uda Arrays

A novel approach for improving antenna bandwidth is described using a 6-element Yagi-Uda array as an example. The new approach applies Central Force Optimization, a deterministic metaheuristic, and Variable Z0 technology, a novel, proprietary design and optimization methodology, to produce an array with 33.09% fractional impedance bandwidth. This array’s performance is compared to its CFO-optimized Fixed Z0counterpart, and to the performance of a 6-ele- ment Dominating Cone Line Search-optimized array. Both CFO-optimized antennas exhibit better performance than the DCLS array, especially with respect to impedance bandwidth. Although the Yagi-Uda antenna was chosen to illustrate this new approach to antenna design and optimization, the methodology is entirely general and can be applied to any antenna against any set of performance objectives.

Determination AHP Analysis of the Virtual Stage-Gate Process in the Global Scale Automotive Design

In this study, it is aimed to determine the ranking importance levels of the stages to be taken into consideration for new product development on a global scale in the automotive design process. New product design activity and stage-gate process differences between local automotive firms (serial production factory and stage-gate department in Turkey) and global automotive companies (serial production factory and stage-gate department in Turkey) are examined comparatively in the research area. In the automotive industry, which has been developing for a century, the question of how the local company products operating in the last sixty years have not been able to spread globally or how to develop global products is the background question of the research. For this purpose, one on one interviews were held with the managers of 3 national and 3 international automotive companies, who worked in the same region and who had previously designed a new vehicle, with design and product development departments.?According to?the data obtained by the AHP (Analytic Hierarchy Process) in the automotive design process, the importance of the criteria that should be taken into account for global product development has revealed. According to the results of the study, it was found that design validation stages were the most important globalization criterion in automotive design process as a new study area. In the comprehensive survey of the study, no other publication has been encountered to measure or evaluate the stages in the automotive design and new product development process in other sectors, including the vehicle industry. As in every industry sector, in the automotive industry, with the new product companies provide market development or competitive advantage. The new product is the life channel of a company and in the realization of this new vehicle;the disciplines of the automotive industry are formed by a hundred years of experience.

Robust Variance-Constrained Design for Uncertain Continuous Stochastic Systems via Output Feedback

This paper studies the problem of robust controller design for linear perturbed continuous stochasticsystems with variance constraints via output feedback. The goal is to design static output feedback controllers suchthat the uncertain system has the desil'ed stability margin and the steady-state variance constraints. The existenceconditions for the desired controllers are discussed, and the analytical expression of these controllers is alsocharacterized. A numerical example is provided to demonstrate the directness and effectiveness of the proposedmethod.

Simulation and prediction of flow patterns in mold filling

The potential of a 3D FDM (Finite Difference Method) computer code was presented, in prediction of flow patterns by modeling the mold filling phenomena through different gating systems. In this code, improvements and modifications were made on the original SOLA VOF and Donor Acceptor algorithms. A more accurate solution procedure for handling free surfaces is developed in order to describe the flows through complicated gating designs. A block casting of 200?mm×200?mm×50?mm with two different gating designs was chosen as the verifying problem. Water analog studies are carried out on these two gating designs. The comparison indicates that computer simulation could be a powerful tool in shaping gating systems.

基于相关性分离的逻辑电路敏感门定位算法

随着CMOS器件特征尺寸进入纳米量级,因高能粒子辐射等造成的电路失效问题日益严重,给电路可靠性带来严峻挑战。现阶段,准确评估集成电路可靠性,并以此为依据对电路进行容错加固,以提高电路系统可靠性变得刻不容缓。然而,由于逻辑电路中存在大量扇出重汇聚结构,由此引发的信号相关性导致可靠性评估与敏感单元定位面临困难。该文提出一种基于相关性分离的逻辑电路敏感门定位算法。先将电路划分为多个独立电路结构(ICS);以ICS为基本单元分析故障传播及信号相关性影响;再利用相关性分离后的电路模块和反向搜索算法精准定位逻辑电路敏感门单元;最后综合考虑面向输入向量空间的敏感门定位及针对性容错加固。实验结果表明,所提算法能准确、高效地定位逻辑电路敏感单元,适用于大规模及超大规模电路的可靠性评估与高效容错设计。

汽车侧裙板数值成型分析及模具设计

汽车侧裙板长度约为1 m,宽度约为0.1 m,卡扣、加强筋、嵌件孔等复杂结构较多,属于大型细长复杂塑件。大型细长复杂塑件成型难度较大,需要采用数值仿真与模具设计相结合的方法,仿真、设计和验证交叉进行、相互渗透。根据产品的特点拟定了3种进浇方案,仿真结果表明,方案Ⅲ(9点进浇)翘曲变形量最小,其值为4.51 mm。通过验证方案Ⅲ的缩水性、填充时间、填充等值线、填充末端时间差及压力差等参数可知,方案Ⅲ填充均匀、末端压力一致、产品无缩水,表面无质量缺陷,为可行方案。根据方案Ⅲ进行模具设计,包括浇注系统、成型零部件、推出机构、冷却系统等。模具设计完毕后对冷却系统进行验证,结果表明,凸凹模的模温温差小于10℃,模温趋于一致,无翘曲变形风险。基于方案Ⅲ的模具设计可作为最终方案,为模具制造和生产提供方向。

基于红外摄像装置的Triniti呼吸门控系统的设计和性能验证

目的通过分析红外摄像装置Triniti呼吸门控系统和腹压带方式下采集的呼吸运动波形及4DCT影像一致性,验证Triniti呼吸门控系统的临床可行性。方法利用CIRS 18023-A呼吸运动模体及配套的CIRS Motion Control软件,导入仿真标准呼吸运动及真实患者的呼吸运动曲线,模拟人体肺部呼吸运动的周期、幅度、频率等,产生不同的呼吸运动模型,并分别用基于腹压带和Triniti呼吸门控系统2种呼吸运动信号触发CT扫描,分析2种装置触发下的4DCT影像一致性,最后根据Triniti系统追踪的呼吸运动,设置门控范围,实现门控治疗。结果2种呼吸运动信号探测装置采集到的呼吸运动波形曲线相关性>0.8(P<0.001),4DCT影像各时相感兴趣区域测量度差异性值为(0.065±0.069)cm,差异无统计学意义(P>0.05)。结论基于红外摄像装置的Triniti呼吸门控系统追踪呼吸精度高,可实现临床呼吸门控治疗,从而有效减少呼吸运动对放射治疗造成的影响。