The conventional circuit model of a bit-stream adder based on sigma delta（∑Δ） modulation is improved with pipeline technology to make it work correctly at high frequencies.The integrated circuit（IC） of the bit-s...The conventional circuit model of a bit-stream adder based on sigma delta（∑Δ） modulation is improved with pipeline technology to make it work correctly at high frequencies.The integrated circuit（IC） of the bit-stream adder is designed with the source coupled logic structure and designed at the transistor level to increase the operating frequency.The IC is fabricated in TSMC＇s 0.18-μm CMOS process.The chip area is 475×570μm^2.A fully digital∑Δsignal generator is designed with a field programmable gate array to test the chip.Experimental results show that the chip meets the function and performance demand of the design,and the chip can work at a frequency of higher than 4 GHz.The noise performance of the adder is analyzed and compared with both theory and experimental results.展开更多
基金Project supported by the National Natural Science Foundation of China(No.60576028).
文摘The conventional circuit model of a bit-stream adder based on sigma delta（∑Δ） modulation is improved with pipeline technology to make it work correctly at high frequencies.The integrated circuit（IC） of the bit-stream adder is designed with the source coupled logic structure and designed at the transistor level to increase the operating frequency.The IC is fabricated in TSMC＇s 0.18-μm CMOS process.The chip area is 475×570μm^2.A fully digital∑Δsignal generator is designed with a field programmable gate array to test the chip.Experimental results show that the chip meets the function and performance demand of the design,and the chip can work at a frequency of higher than 4 GHz.The noise performance of the adder is analyzed and compared with both theory and experimental results.
