The Immunity of Evolvable Digital Circuits to ESD Interference

With the rapid development of semiconductor technology and the increasing proliferation of emission sources, digital circuits are frequently used in harsh and hostile electromagnetic environments. Electrostatic Discharge （ESD） interferences are gradually gaining prominence, resulting in performance degradations, malfunctions and disturbances in component and/or system level applications. Conventional solutions to such problems are shielding, filtering and grounding. This paper proposes a novel Evolvable Digital Circuit （EDC） for intrinsic immunity. The key idea is motivated by the noise-robustness and fault-tolerance of the biological system. First, the architecture of the EDC is designed based on the cell structure. Then, ESD immunity tests are carried out on the most fragile element of the EDC in operation. Based on the results, fault models are also presented to simulate different functional disturbances. Finally, the immunity of the EDC is evaluated while it is exposed to a variety of simulated environments. The results which demonstrate a graceful immunity to ESD interference are presented.

Bounded Algebra and Current-Mode Digital Circuits

This paper proposes two bounded arithmetic operations, which areeasily realized with current signals. Based on these two operations, a bounded algebra system suitable for describing current-mode digital circuits is developed andits relationship with the Boolean algebra, which is suitable for representing voltagemode digital circuits, is investigated. Design procedure for current-mode circuitsusing the proposed algebra system is demonstrated on a number of common circuit elements which are used to realize arithmetic operations, such as adders andmultipliers.

FAULT DETECTION FOR MULTIPLE-VALUED LOGIC CIRCUITS WITH FANOUT-FREE

The single fault and multiple fault detections for multiple-valued logic circuits are studied in this paper. Firstly, it is shown that the cardinality of optimal single fault test set for fanout-free m-valued circuits with n primary inputs is not more than n + 1, for linear tree circuits is two, and for multiplication modulo circuits is two if n is an odd number or if n is an even number and m ＞ 3, where the optimal test set of a circuit has minimal number of test vectors. Secondly,it is indicated that the cardinality of optimal multiple fault test set for linear tree circuits with n primary inputs is 1 + [n/(m - 1)], for multiplication modulo circuits is n+ 1, for fanout-free circuits that consist of 2-input linear tree circuits and 2-input multiplication modulo circuits is not greater than n+ 1, where [x] denotes the smallest integer greater than or equal to x. Finally,the single fault location approaches of linear tree circuits and multiplication modulo circuits are presented, and all faults in the two types of circuits can be located by using a test set with n + 1 vectors.

Area-Optimized BCD-4221 VSLI Adder Architecture for High-Performance Computing

Decimal arithmetic circuits are promising to provide a solution for accurate decimal arithmetic operations which are not possible with binary arithmetic circuits.They can be used in banking,commercial and financial transactions,scientific measurements,etc.This article presents the Very Large Scale Integration(VLSI)design of Binary Coded Decimal(BCD)-4221 area-optimized adder architecture using unconventional BCD-4221 representation.Unconventional BCD number representations such as BCD4221 also possess the additional advantage of more effectively representing the 10's complement representation which can be used to accelerate the decimal arithmetic operations.The design uses a binary Carry Lookahead Adder(CLA)along with some other logic blocks which are required to perform internal calculations with BCD-4221 numbers.The design is verified by using Xilinx Vivado 2016.1.Synthesis results have been obtained by Cadence Genus16.1 synthesis tool using 90 nm technology.The performance parameters such as area,power,delay,and area-delay Product(ADP)are compared with earlier reported circuits.Our proposed circuit shows significant area and ADP improvement over existing designs.

Design of Polymorphic Operators for Efficient Synthesis of Multifunctional Circuits

Systematic effort dedicated to the exploration of feasible ways how to permanently come up with even more space-efficient implementation of digital circuits based on conventional CMOS technology node may soon reach the ultimate point, which is mostly given by the constraints associated with physical scaling of fundamental electronic components. One of the possible ways of how to mitigate this problem can be recognized in deployment of multifunctional circuit elements. In addition, the polymorphic electronics paradigm, with its considerable independence on a parti- cular technology, opens a way how to fulfil this objective through the adoption of emerging semiconductor materials and advanced synthesis methods. In this paper, main attention is focused on the introduction of polymorphic operators (i.e. digital logic gates) that would allow to further increase the efficiency of multifunctional circuit synthesis techniques. Key aspect depicting the novelty of the proposed approach is primarily based on the intrinsic exploitation of components with ambi- polar conduction property. Finally, relevant models of the polymorphic operators are presented in conjunction with the experimental results.

Testing Cross-Talk Induced Delay Faults in Digital Circuit Based on Transient Current Analysis

The delay fault induced by cross-talk effect is one of the difficult problems in the fault diagnosis of digital circuit. An intelligent fault diagnosis based on IDDT testing and support vector machines （SVM） classifier was proposed in this paper. Firstly, the fault model induced by cross-talk effect and the IDDT testing method were analyzed, and then a delay fault localization method based on SVM was presented. The fault features of the sampled signals were extracted by wavelet packet decomposition and served as input parameters of SVM classifier to classify the different fault types. The simulation results illustrate that the method presented is accurate and effective, reaches a high diagnosis rate above 95%.

A review on the design of ternary logic circuits

A multi-valued logic system is a promising alternative to traditional binary logic because it can reduce the complexity,power consumption, and area of circuit implementation. This article briefly summarizes the development of ternary logic and its advantages in digital logic circuits. The schemes, characteristics, and application of ternary logic circuits based on CMOS, CNTFET, memristor, and other devices and processes are reviewed in this paper, providing some reference for the further research and development of ternary logic circuits.

Characterization of Fundamental Logics for the Sub-Threshold Digital Design

Digital circuits operating in the sub-threshold regime consume the least energy. The strict energy constraints are desired in the applications which work at the lowest possible supply voltage. On the other hand, the conventional design flow utilizes the technology library provided by the foundry with a fixed voltage boundary, which causes problems when the supply scales down to the sub-threshold regime. In this paper, we present a design methodology to characterize the existing cell library with Liberty NCX to facilitate the standard design flow. It is demonstrated in 0.13 μm complementary metal-oxide-semiconductor （CMOS） technology with the supply voltage of 300 mV.

Evolutionary Design of Fault-Tolerant Digital Circuit Based on Cartesian Genetic Programming

In many areas, reliability of the digital circuits has become the key factor to restrict circuit development. Fault-tolerant design is the commonly used method to improve the reliability of digital circuits. The current fault-tolerant design methods are based on triple modular redundancy( TMR) or multiple modular redundancy( MMR). These redundancy designs rely on the experience of the designers,and the designed circuits have poor adaptabilities to a complex environment. However, evolutionary design of digital circuits does not rely on prior knowledge. During the evolution, some novel and optimal circuit topologies can be found, and the evolved circuits can feature strong adaptive capacities. Based on Cartesian genetic programming( CGP), a novel method for designing fault-tolerant digital circuits by evolution is proposed,key steps of the evolution are introduced,influences of function sets on evolution are investigated,and as a preliminary result,an evolved full adder with high fault-tolerance is shown.

Design of Digital Circuit Experiment Course Based on FPGA

With the development of integrated circuit, the content of digital circuit experiment course is constantly updated. In order to keep up with the development trend of the Times and make students’ professional knowledge meet the needs of the industry, the school adopts the FPGA experimental platform to carry out teaching reform from the two aspects of platform and experiment, and carry out reasonable experimental planning to enrich the experimental content. In this paper, the traditional knowledge points of logic algebra, trigger, timer, counter, decoder and digital tube are organically combined, and the digital clock system is designed and realized. The practice shows that the combination of modern design method and traditional digital circuit teaching method can play a good teaching effect. In this way, students can also fully learn, understand and skillfully use the new technology in the experiment, and in the process of building a comprehensive understanding of digital circuits.

VST/DL Digital Circuit Testing & Analytical System

An important means for digital circuit analysis, design. maintenance and production is the IC chip test and analysis. With digital circuit application prevailing today, the automatic test and analysis of digital circuits is going to play a more important role. It can save a great deal of time and cost for the maintenance of equipment and can also provide correst analytical data for designers.

Research on Digital and Analog Electronic Experiment Teaching Course Management based on UltraLab Network Experiment Platform

Digital circuit and analog circuit courses are basic courses for students of science and engineering universities. Among them,the practical courses are of great significance for students to master the knowledge of electronics. In order to make teachers teaching more efficiently and students studying more quickly,how to update the experimental course in teaching reform is the key point. This paper analyzing the present situation of teaching in the digital circuit and analog circuit courses,the teaching questions in universities. On the basis of it,the innovation measures of experimental teaching methods and contents are discussed. Our school tries to introduce the UltraLab network experiment platform,reform and optimize the teaching methods of related courses.And it’ s accelerating the construction and development of emerging engineering education’ s process,reducing effectively the teacher’s time for managing in equipment,improving the students’ ability to use instruments.

Cultural Algorithm for Minimization of Binary Decision Diagram and Its Application in Crosstalk Fault Detection

The binary decision diagrams （BDDs） can give canonical representation to Boolean functions; they have wide applications in the design and verification of digital systems. A new method based on cultural algorithms for minimizing the size of BDDs is presented in this paper. First of all, the coding of an individual representing a BDDs is given, and the fitness of an individual is defined. The population is built by a set of the individuals. Second, the implementations based on cultural algorithms for the minimization of BDDs, i.e., the designs of belief space and population space, and the designs of acceptance function and influence function, are given in detail. Third, the fault detection approaches using BDDs for digital circuits are studied. A new method for the detection of crosstalk faults by using BDDs is presented. Experimental results on a number of digital circuits show that the BDDs with small number of nodes can be obtained by the method proposed in this paper, and all test vectors of a fault in digital circuits can also be produced.

A New Method for the Detections of Multiple Faults Using Binary Decision Diagrams

With the complexity of integrated circuits is continually increasing, a local defect in circuits may cause multiple faults. The behavior of a digital circuit with a multiple fault may significantly differ from that of a single fault. A new method for the detection of multiple faults in digital circuits is presented in this paper, the method is based on binary decision diagram （BDD）. First of all, the BDDs for the normal circuit and faulty circuit are built respectively. Secondly, a test BDD is obtained by the XOR operation of the BDDs corresponds to normal circuit and faulty circuit. In the test BDD, each input assignment that leads to the leaf node labeled 1 is a test vector of multiple faults. Therefore, the test set of multiple faults is generated by searching for the type of input assignments in the test BDD. Experimental results on some digital circuits show the feasibility of the approach presented in this paper.

FPGA-based high resolution DPWM control circuit

Two improved structures of high resolution digital pulse width modulator(DPWM) control circuit are proposed. Embedded digital clock manager(DCM) blocks and digital programmable delay circuits are employed as the basic resources to construct the field-programmable gate array(FPGA)-based DPWM implementations. Detailed schemes are illustrated and the circuits have been successfully implemented on the Artix-7 FPGA device developed by Xilinx. Experimental results show that when the basic clock operates at the frequency of 200 MHz, the resolutions of the two approaches can reach 625 ps and 500 ps, respectively. Besides,the presented schemes possess other merits including flexible resolution, strong versatility and relatively good stability.

Design of 4.25 Gbps Small Form-factor Pluggable(SFP) Transceiver

Compact, hot-pluggable, and data-agnostic, SFP modules bring up to 4.25 Gbps to a flexible new form factor. The SFP transceiver which is the core device of optical communication is always the research focus in the field of optical communication for both telecommunication and data communication applications. The working principles of SFP including the transmitter components, the receiver components and the microcontroller are discussed in detail. The basic theory of high-speed signal and the concept of high - speed circuit, high-speed board design techniques are presented. A new design of high performance, cost effective SFP transceiver and PCB layout are also presented. The performance of the transceiver is analyzed and the characteristics of the sample are coincident with the expected ones. The status of the transceiver can be monitored and controlled by F C bus through the interface in real time. This transceiver can meet the requirement of SFF-8472.

Accelerating hybrid and compact neural networks targeting perception and control domains with coarse-grained dataflow reconfiguration

Driven by continuous scaling of nanoscale semiconductor technologies,the past years have witnessed the progressive advancement of machine learning techniques and applications.Recently,dedicated machine learning accelerators,especially for neural networks,have attracted the research interests of computer architects and VLSI designers.State-of-the-art accelerators increase performance by deploying a huge amount of processing elements,however still face the issue of degraded resource utilization across hybrid and non-standard algorithmic kernels.In this work,we exploit the properties of important neural network kernels for both perception and control to propose a reconfigurable dataflow processor,which adjusts the patterns of data flowing,functionalities of processing elements and on-chip storages according to network kernels.In contrast to stateof-the-art fine-grained data flowing techniques,the proposed coarse-grained dataflow reconfiguration approach enables extensive sharing of computing and storage resources.Three hybrid networks for MobileNet,deep reinforcement learning and sequence classification are constructed and analyzed with customized instruction sets and toolchain.A test chip has been designed and fabricated under UMC 65 nm CMOS technology,with the measured power consumption of 7.51 mW under 100 MHz frequency on a die size of 1.8×1.8 mm^2.

TEST OF BOARD-LEVEL BOUNDARY SCAN INTEGRITY

The IEEE Standard 1149.1 boundary scan (BS) implementation provides the internal access required for testing the digital printed circuit board (PCB). However, the integrity of the boundary scan test infrastructure should be tested first to guarantee the validation of the results of the rest functional test and diagnosis. This paper describes the fault models and test principles of the BS test access port (TAP) lines on PCBs. A test algorithm with high fault coverage and short time is then presented for the PCB on which all ICs are BS ones.

Design of Hybrid True Random Number Generator for Cryptographic Applications

In real-time applications,unpredictable random numbers play a major role in providing cryptographic and encryption processes.Most of the existing random number generators are embedded with the complex nature of an amplifier,ring oscillators,or comparators.Hence,this research focused more on implementing a Hybrid Nature of a New Random Number Generator.The key objective of the proposed methodology relies on the utilization of True random number generators.The randomness is unpredictable.The additions of programmable delay lines will reduce the processing time and maintain the quality of randomizing.The performance comparisons are carried out with power,delay,and lookup table.The proposed architecture was executed and verified using Xilinx.The Hybrid TRNG is evaluated under simulation and the obtained results outperform the results of the conventional random generators based on Slices,area and Lookup Tables.The experimental observations show that the proposed Hybrid True Random Number Generator(HTRNG)offers high operating speed and low power consumption.

Test Vector Optimization Using Pocofan-Poframe Partitionin

This paper presents an automated POCOFAN-POFRAME algorithm thatpartitions large combinational digital VLSI circuits for pseudo exhaustive testing. In thispaper, a simulation framework and partitioning technique are presented to guide VLSIcircuits to work under with fewer test vectors in order to reduce testing time and todevelop VLSI circuit designs. This framework utilizes two methods of partitioningPrimary Output Cone Fanout Partitioning (POCOFAN) and POFRAME partitioning todetermine number of test vectors in the circuit. The key role of partitioning is to identifyreconvergent fanout branch pairs and the optimal value of primary input node N andfanout F partitioning using I-PIFAN algorithm. The number of reconvergent fanout andits locations are critical for testing of VLSI circuits and design for testability. Hence, theirselection is crucial in order to optimize system performance and reliability. In the presentwork, the design constraints of the partitioned circuit considered for optimizationincludes critical path delay and test time. POCOFAN-POFRAME algorithm uses theparameters with optimal values of circuits maximum primary input cone size (N) andminimum fan-out value (F) to determine the number of test vectors, number of partitionsand its locations. The ISCAS’85 benchmark circuits have been successfully partitioned,the test results of C499 shows 45% reduction in the test vectors and the experimentalresults are compared with other partitioning methods, our algorithm makes fewer testvectors.