Channel capacity and digital modulation schemes in correlated Weibull fading channels with nonidentical statistics

The novel closed-form expressions for the average channel capacity of dual selection diversity is presented, as well as, the bit-error rate （BER） of several coherent and noncoherent digital modulation schemes in the correlated Weibull fading channels with nonidentical statisticS. The results are expressed in terms of Meijer＇s Gfunction, which can be easily evaluated numerically. The simulation results are presented to validate the proposed theoretical analysis and to examine the effects of the fading severity on the concerned quantities.

A new method of demodulating the digital frequency modulation signals

A new method of estimating the frequency-known signals from the strong background noise was presented first. Then the new method was used in the demodulation of the digital frequency modulation (FSK) signals. The new demodulation method can complete the demodulation of the FSK signals only with the carrier frequency and without any carrier phase information. The simulation results show that the performance of anti-noise of the new method is better than that of the incoherent demodulation method and the fluctuation of the carrier phase has little effect on the new method. So the new demodulation method has a fine prospect in the practical applications.

A novel adaptive classification scheme for digital modulations in satellite communication

To make the modulation classification system more suitable for signals in a wide range of signal to noise ratios （SNRs）, a novel adaptive modulation classification scheme is presented in this paper. Differ-ent from traditional schemes, the proposed scheme employs a new SNR estimation algorithm for small samples before modulation classification, which makes the modulation classifier work adaptively according to estimated SNRs. Furthermore, it uses three efficient features and support vector machines （SVM） in modulation classification. Computer simulation shows that the scheme can adaptively classify ten digital modulation types （i.e. 2ASK, 4ASK, 2FSK, 4FSK, 2PSK, 4PSK, 16QAM, TFM, π/4QPSK and OQPSK） at SNRS ranging from 0dB to 25dB and success rates are over 95% when SNR is not lower than 3dB. Accuracy, efficiency and simplicity of the proposed scheme are obviously improved, which make it more adaptive to engineering applications.

Superpixel-Based Complex Field Modulation Using a Digital Micromirror Device for Focusing Light through Scattering Media

We present a digital micromirror device（DMD） based superpixel method for focusing light through scattering media by modulating the complex field of incident light. Firstly, we numerically and experimentally investigate focusing light through a scattering sample using the superpixel methods with different target complex fields.Then, single-point and multiple-point focusing experiments are performed using this superpixel-based complex modulation method. In our experiment, up to 71.5% relative enhancement is realized. The use of the DMDbased superpixel method for the control of the complex field of incident light opens an avenue to improve the enhancement of focusing light through scattering media.

Digital modulation classification using multi-layer perceptron and time-frequency features

Considering that real communication signals corrupted by noise are generally nonstationary, and timefrequency distributions are especially suitable for the analysis of nonstationary signals, time-frequency distributions are introduced for the modulation classification of communication signals： The extracted time-frequency features have good classification information, and they are insensitive to signal to noise ratio （SNR） variation. According to good classification by the correct rate of a neural network classifier, a multilayer perceptron （MLP） classifier with better generalization, as well as, addition of time-frequency features set for classifying six different modulation types has been proposed. Computer simulations show that the MLP classifier outperforms the decision-theoretic classifier at low SNRs, and the classification experiments for real MPSK signals verify engineering significance of the MLP classifier.

Realizable Hardware-Based Method for Digital Modulation Classification

A new method suited for hardware implementation is developed to classify 8 different digital modulation types with raised cosine base-band impulse without knowing the carrier frequency and symbol timing. The normalized histogram of stagnation points for instantaneous parameters is used to recognize both ideal rectangular and raised cosine base-band digital signals. Carrier frequency estimation is used to enhance the recognition rate of phase-modulated signals. In the condition of 10 dB signal noise ratio （SNR）, the recognizing rate is over 80% . The new algorithm is suited for hardware implementation.

Piecewise linear detection for direct superposition modulation

Considering high-order digital modulation schemes, the bottleneck in consumer products is the detector rather than the modulator. The complexity of the optimal a posteriori probability （APP） detector increases exponentially with respect to the number of modulated bits per data symbol. Thus, it is necessary to develop low-complexity detection algorithms with an APP-like performance, especially when performing iterative detection, for example in conjunction with bit interleaved coded modulation. We show that a special case of superposition modulation, dubbed Direct Superposition Modulation （DSM）, is particularly suitable for complexity reduction at the receiver side. As opposed to square QAM, DSM achieves capacity without active signal shaping. The main contribution is a low-cost detection algorithm for DSM, which enables iterative detection by taking a priori information into account. This algorithm exploits the approximate piecewise linear behavior of the soft outputs of an APP detector over the entire range of detector input values. A theoretical analysis and simulation results demonstrate that at least max-log APP performance can be reached, while the complexity is significantly reduced compared to classical APP detection.

Integration and verification case of IP-core based system on chip design

In this paper, the design and verification process of an automobile-engine-fan control system on chip （SoC） are introduced. The SoC system, SHU-MV08, reuses four new intellectual property （IP） cores and the design flow is accomplished with 0.35 btm chartered CMOS technology. Some special functions of IP cores, the detailed integration scheme of four IP cores, and the verification method of the entire SoC are presented. To settle the verification problems brought by analog IP cores, NanoSim based chip-level mixed-signal verification method is introduced. The verification time is greatly reduced and the first tape-out achieves success which proves the validity of our design.

Design of low-power high-frequency digital controlled DC-DC switching power converter

This paper models a low-power high-frequency digitally controlled synchronous rectifier （SR） OUCK converter. The converter is a hybrid system with three operation modes. Digital PID controler is used. Key problems such as quantization resolution of digital pulse-width modulation （DPWM） and steady-state limit cycles of digital control switching model power supply （SMPS） are discussed, with corresponding solutions presented. Simulation of a digital control synchronous buck is performed with a fixed-point algorithm. The results show that the described approach enables high-speed dynamic performance.

Symbol detection based on Voronoi surfaces with emphasis on superposition modulation

A challenging task when applying high-order digital modulation schemes is the complexity of the detector. Particularly, the complexity of the optimal a posteriori probability （APP） detector increases exponentially with respect to the number of bits per data symbol. This statement is also true for the Max-Log-APP detector, which is a common simplification of the APP detector. Thus it is important to design new detection algorithms which combine a sufficient performance with low complexity. In this contribution, a detection algorithm for two- dimensional digital modulation schemes which cannot be split-up into real and imaginary parts （like phase shift keying and phase-shifted snperposition modulation （PSM）） is proposed with emphasis on PSM with equal power allocation. This algorithm exploits the relationship between Max-Log-APP detection and a Voronoi diagram to determine planar surfaces of the soft outputs over the entire range of detector input values. As opposed to state-of-the-art detectors based on Voronoi surfaces, a priori information is taken into account, enabling iterative processing. Since the algorithm achieves Max-Log-APP performance, even in the presence of a priori information, this implies a great potential for complexity reduction compared to the classical APP detection.

Digital modulation recognition based on instantaneous information

A new digital modulation recognition algorithm based on the instantaneous information is proposed to improve the recognition success rate in the low signal noise ratio （SNR）. First denoising of the instantaneous information is optimized by wavelet filter, which can improve the recognition ability at low SNR. Besides the existing 3 key feature parameters, 3 new key feature parameters are proposed to be used as the decision criteria for identifying different types of digital modulation, which simplifies the recognition process and improves the recognition ability at low SNR. The simulations demonstrate that all modulation types of interest have been classified with success rate of no lower than 99 % when SNR is 10dB. Even if the SNR is lower than 5 dB, the success rate is over 95.4% for most of the modulation types.

Dynamic infrared scene simulation using grayscale modulation of digital micro-mirror device

Dynamic infrared scene simulation is for discovering and solving the problems encountered in designing, developing and manufacturing infrared imaging guidance weapons. The infrared scene simulation is explored by using the digital grayscale modulation method. The infrared image modulation model of a digital micro-mirror device （DMD） is established and then the infrared scene simulator prototype which is based on DMD grayscale modulation is developed. To evaluate its main parameters such as resolution, contrast, minimum temperature difference, gray scale, various DMD subsystems such as signal decoding, image normalization, synchronization drive, pulse width modulation （PWM） and DMD chips are designed. The infrared scene simulator is tested on a certain infrared missile seeker. The test results show preliminarily that the infrared scene simulator has high gray scale, small geometrical distortion and highly resolvable imaging resolution and contrast and yields high-fidelity images, thus being able to meet the requirements for the infrared scene simulation inside a laboratory.

Carrier frequency and symbol rate estimation based on cyclic spectrum

Carrier frequency and symbol rate estimation are the main contents of parameter estimation,which is the basis of modulation recognition and further processing of signals especially in non-cooperative communication.With the development of wireless communication,the signal transmission environment has become increasingly bad,causing more difficulties in parameter estimation.It is well known that the signal cycle spectrum is robust to noises and signal parameters are closely related.In practice,it is impossible to calculate the cyclic spectrum of infinite length data signals.When using finite length data to obtain a cycle spectrum,the truncation noise is induced,resulting in interference.It is necessary to overcome the influence of noises in order to improve the detection ability of discrete spectral lines.An improved method of the discrete spectral line extraction algorithm is proposed by reflecting the amplitude advantage of discrete spectral lines through salient features of continuous noises in discrete spectral line neighborhood.

FPGA-based high resolution DPWM control circuit

Two improved structures of high resolution digital pulse width modulator(DPWM) control circuit are proposed. Embedded digital clock manager(DCM) blocks and digital programmable delay circuits are employed as the basic resources to construct the field-programmable gate array(FPGA)-based DPWM implementations. Detailed schemes are illustrated and the circuits have been successfully implemented on the Artix-7 FPGA device developed by Xilinx. Experimental results show that when the basic clock operates at the frequency of 200 MHz, the resolutions of the two approaches can reach 625 ps and 500 ps, respectively. Besides,the presented schemes possess other merits including flexible resolution, strong versatility and relatively good stability.

Design and development of high linearity millimeter wave traveling-wave tube for satellite communications

The linearity of the traveling-wave tube is a very important characteristic for a modern communication system. To improve the linearity of the traveling-wave tube at no expense of the saturated output power and overall efficiency, a modified pitch profile combined with a small adjustment of operating parameters is proposed. The optimal design of the helix circuit is evaluated theoretically by a large signal analysis, and the experimental test is also carried out to make a comparison of performance between the novel and original designed traveling-wave tubes. The experiments show that the saturated output powers and efficiencies of these two tubes are close to each other, while the linearity of the traveling-wave tube is obviously improved. The total phase shift and AM/PM conversion at saturation of the novel tube, averaged over the operating band, are only 30.6°/d B and 2.5°/d B, respectively, which are 20.1°/d B and 1.6°/d B lower than those of the original tube, respectively. Moreover, the third-order intermodulation of the novel tube is up to 2.2 d Bc lower than that of the original tube.

FPGA based digital phase-coding quantum key distribution system

Quantum key distribution （QKD） is a technology with the potential capability to achieve information-theoretic security. Phase- coding is an important approach to develop practical QKD systems in fiber channel. In order to improve the phase-coding modulation rate, we proposed a new digital-modulation method in this paper and constructed a compact and robust prototype of QKD system using currently available components in our lab to demonstrate the effectiveness of the method. The system was deployed in laboratory environment over a 50 km fiber and continuously operated during 87 h without manual interaction. The quantum bit error rate （QBER） of the system was stable with an average value of 3.22% and the secure key generation rate is 8.91 kbps. Although the modulation rate of the photon in the derno system was only 200 MHz, which was limited by the Faraday- Michelson interferometer （FMI） structure, the proposed method and the field programmable gate array （FPGA） based electronics scheme have a great potential for high speed QKD systems with Giga-bits/second modulation rate.

Speckle noise reduction in digital holography with spatial light modulator and nonlocal means algorithm

An integrated method based on optical and digital image processing is presented to suppress speckle in digital holography. A spatial light modulator is adopted to introduce random phases to the illuminating beam. Multiple holograms are reconstructed and superimposed, and the intensity is averaged to smooth the noise. The adaptive algorithm based on the nonlocal means is designed to further suppress the speckle. The presented method is compared with other methods reduction is improved, and the proposed method is effective The experimental results show that speckle and feasible.

A 1.2-V,84-dB∑△ADM in 0.18-μm digital CMOS technology

A low power and low voltage∑△analog-to-digital modulator is realized with digital CMOS technology, which is due to full compensated depletion mode capacitors.Compared with mixed signal technology,this type of modulator is more compatible for pure digital applications.A pseudo-two-stage class-AB OTA is used in switchedcapacitor integrators for low voltage and low power.The modulator is realized in standard SMIC 0.18μm 1P6M digital CMOS technology.Measured results show that with 1.2 V supply voltage and a 6 MHz sample clock,the dynamic range of the modulator is 84 dB and the total power dissipation is 2460μW.

Micro EEG/ECG signal's chopper-stabilization amplifying chip for novel drycontact electrode

Facing the body＇s EEG（electroencephalograph, 0.5–100 Hz, 5–100 μV） and ECG＇s（electrocardiogram,〈 100 Hz, 0.01–5 mV） micro signal detection requirement, this paper develops a pervasive application micro signal detection ASIC chip with the chopping modulation/demodulation method. The chopper-stabilization circuit with the RRL（ripple reduction loop） circuit is to suppress the ripple voltage, which locates at the single-stage amplifier＇s outputting terminal. The single-stage chopping core＇s noise has been suppressed too, and it is beneficial for suppressing noises of post-circuit. The chopping core circuit uses the PFB（positive feedback loop） to increase the inputting resistance, and the NFB（negative feedback loop） to stabilize the 40 dB intermediate frequency gain. The cascaded switch-capacitor sample/hold circuit has been used for deleting spike noises caused by non-ideal MOS switches, and the VGA/BPF（voltage gain amplifier/band pass filter） circuit is used to tune the chopper system＇s gain/bandwidth digitally. Assisted with the designed novel dry-electrode, the real test result of the chopping amplifying circuit gives some critical parameters： 8.1 μW/channel, 0.8 μVrms（@band-widthD100 Hz）, 4216–11220 times digitally tuning gain range, etc. The data capture system uses the NI CO＇s data capturing DAQmx interface,and the captured micro EEG/ECG＇s waves are real-time displayed with the PC-Labview. The proposed chopper system is a unified EEG/ECG signal＇s detection instrument and has a critical real application value.