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A fast combination calibration of foreground and background for pipelined ADCs 被引量:1
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作者 孙可旭 何乐年 《Journal of Semiconductors》 EI CAS CSCD 2012年第6期84-94,共11页
This paper describes a fast digital calibration scheme for pipelined analog-to-digital converters(ADCs). The proposed method corrects the nonlinearity caused by finite opamp gain and capacitor mismatch in multiplyin... This paper describes a fast digital calibration scheme for pipelined analog-to-digital converters(ADCs). The proposed method corrects the nonlinearity caused by finite opamp gain and capacitor mismatch in multiplying digital-to-analog converters(MDACs).The considered calibration technique takes the advantages of both foreground and background calibration schemes.In this combination calibration algorithm,a novel parallel background calibration with signal-shifted correlation is proposed,and its calibration cycle is very short.The details of this technique are described in the example of a 14-bit 100 Msample/s pipelined ADC.The high convergence speed of this background calibration is achieved by three means.First,a modified 1.5-bit stage is proposed in order to allow the injection of a large pseudo-random dithering without missing code.Second,before correlating the signal,it is shifted according to the input signal so that the correlation error converges quickly.Finally,the front pipeline stages are calibrated simultaneously rather than stage by stage to reduce the calibration tracking constants.Simulation results confirm that the combination calibration has a fast startup process and a short background calibration cycle of 2×2^(21) conversions. 展开更多
关键词 background calibration capacitor mismatch and gain calibration digital calibration foreground calibration pipelined analog-to-digital converter signal-shifted correlation
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A 14-bit 100-MS/s CMOS pipelined ADC with 11.3 ENOB
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作者 王科 范超杰 +1 位作者 周健军 潘文捷 《Journal of Semiconductors》 EI CAS CSCD 2013年第8期172-176,共5页
This paper demonstrates a 14-bit 100-MS/s pipelined analog-to-digital converter(ADC) in 0.18μm CMOS process with a 1.8 V supply voltage.A fast foreground digital calibration mechanism is employed to correct capacit... This paper demonstrates a 14-bit 100-MS/s pipelined analog-to-digital converter(ADC) in 0.18μm CMOS process with a 1.8 V supply voltage.A fast foreground digital calibration mechanism is employed to correct capacitor mismatches.The ADC implements an SHA-less 3-bit front-end to reduce the size of the sampled capacitor. The presented ADC achieves a 70.02 dB signal-to-noise distortion ratio(SNDR) and an 87.5 dB spurious-free dynamic range(SFDR) with a 30.7 MHz input signal,while maintaining over 66 dB SNDR and 76 dB SFDR up to 200 MHz input.The power consumption is 543 mW and a total die area of 3 x 4 mm2 is occupied. 展开更多
关键词 pipelined ADC SHA-less MDAC residue amplifier digital calibration
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