Structure Design Considerations of a Sub-50nm Self-Aligned Double-Gate MOSFET

A comprehensive way to design a sub 50nm SADG MOSFET with the ability of being fabricated by improved CMOS technique is described.Under this way,the gate length and thickness of Si island of DG device show many different scaling limits for various elements.Meanwhile,the spacer insulator shows a kind of width thickness on device drain current and circuit speed.A model about that effect is developed and offers design consideration for future.A new design of channel doping profile,called SCD,is also discussed here in detail.The DG device with SCD can achieve a good balance between the volume inversion operation mode and the control of V th .Finally,a guideline to make a SADG MOSFET is presented.

Modeling the drain current and its equation parameters for lightly doped symmetrical double-gate MOSFETs

A 2D model for the potential distribution in silicon film is derived for a symmetrical double gate MOS- FET in weak inversion. This 2D potential distribution model is used to analytically derive an expression for the subthreshold slope and threshold voltage. A drain current model for lightly doped symmetrical DG MOSFETs is then presented by considering weak and strong inversion regions including short channel effects, series source to drain resistance and channel length modulation parameters. These derived models are compared with the simulation results of the SILVACO （Atlas） tool for different channel lengths and silicon film thicknesses. Lastly, the effect of the fixed oxide charge on the drain current model has been studied through simulation. It is observed that the obtained analytical models of syrnmetrical double gate MOSFETs are in good agreement with the simulated results for a channel length to silicon film thickness ratio greater than or equal to 2.

A Finite Volume Method for the Multi Subband Boltzmann Equation with Realistic 2D Scattering in Double Gate MOSFETs

We propose a deterministic solver for the time-dependent multi-subband Boltzmann transport equation(MSBTE)for the two dimensional(2D)electron gas in double gate metal oxide semiconductor field effect transistors(MOSFETs)with flared out source/drain contacts.A realistic model with six-valleys of the conduction band of silicon and both intra-valley and inter-valley phonon-electron scattering is solved.We propose a second order finite volume method based on the positive and flux conservative(PFC)method to discretize the Boltzmann transport equations(BTEs).The transport part of the BTEs is split into two problems.One is a 1D transport problem in the position space,and the other is a 2D transport problem in the wavevector space.In order to reduce the splitting error,the 2D transport problem in the wavevector space is solved directly by using the PFC method instead of splitting into two 1D problems.The solver is applied to a nanoscale double gate MOSFET and the current-voltage characteristic is investigated.Comparison of the numerical results with ballistic solutions show that the scattering influence is not ignorable even when the size of a nanoscale semiconductor device goes to the scale of the electron mean free path.

Device and circuit analysis of a sub 20 nm double gate MOSFET with gate stack using a look-up-table-based approach

In this paper, we explore the possibility of mapping devices designed in TCAD environment to its modeled version developed in cadence virtuoso environment using a look-up table （LUT） approach. Circuit simu- lation of newly designed devices in TCAD environment is a very slow and tedious process involving complex scripting. Hence, the LUT based modeling approach has been proposed as a faster and easier alternative in ca- dence environment. The LUTs are prepared by extracting data from the device characteristics obtained from device simulation in TCAD. A comparative study is shown between the TCAD simulation and the LUT-based alternative to showcase the accuracy of modeled devices. Finally the look-up table approach is used to evaluate the perform- ance of circuits implemented using 14 nm nMOSFET.

Performance analysis of SiGe double-gate N-MOSFET

The major purpose of this paper is to find an alternative configuration that not only minimizes the limitations of single-gate（SG） MOSFETs but also provides the better replacement for future technology.In this paper,the electrical characteristics of SiGe double-gate N-MOSFET are demonstrated and compared with electrical characteristics of Si double-gate N-MOSFET.Furthermore,in this paper the electrical characteristics of Si doublegate N-MOSFET are demonstrated and compared with electrical characteristics of Si single-gate N-MOSFET.The simulations are carried out for the device at different operational voltages using Cogenda Visual TCAD tool.Moreover,we have designed its structure and studied both Id-Vg characteristics for different voltages namely 0.05,0.1,0.5,0.8,1 and 1.5 V and Id-Vd characteristics for different voltages namely 0.1,0.5,1 and 1.5 V at work functions 4.5,4.6 and 4.8 eV for this structure.The performance parameters investigated in this paper are threshold voltage,DIBL,subthreshold slope,GIDL,volume inversion and MMCR.

A compact model for single material double work function gate MOSFET

An analytical surface potential model for the single material double work function gate （SMDWG） MOSFET is developed based on the exact resultant solution of the two-dimensional Poisson equation. The model includes the effects of drain biases, gate oxide thickness, different combinations of S-gate and D-gate length and values of substrate doping concentration. More attention has been paid to seeking to explain the attributes of the SMDWG MOSFET, such as suppressing drain-induced barrier lowering （DIBL）, accelerating carrier drift velocity and device speed. The model is verified by comparison to the simulated results using the device simulator MEDICI. The accuracy of the results obtained using our analytical model is verified using numerical simulations. The model not only offers the physical insight into device physics but also provides the basic designing guideline for the device.