Structure Design Considerations of a Sub-50nm Self-Aligned Double-Gate MOSFET

A comprehensive way to design a sub 50nm SADG MOSFET with the ability of being fabricated by improved CMOS technique is described.Under this way,the gate length and thickness of Si island of DG device show many different scaling limits for various elements.Meanwhile,the spacer insulator shows a kind of width thickness on device drain current and circuit speed.A model about that effect is developed and offers design consideration for future.A new design of channel doping profile,called SCD,is also discussed here in detail.The DG device with SCD can achieve a good balance between the volume inversion operation mode and the control of V th .Finally,a guideline to make a SADG MOSFET is presented.

Threshold Voltage Model of a Double-Gate MOSFET with Schottky Source and Drain

A quasi two-dimensional （2D） analytical model of a double-gate （DG） MOSFET with Schottky source/drain is developed based on the Poisson equation.The 2D potential distribution in the channel is calculated.An expression for threshold voltage for a short-channel DG MOSFET with Schottky S/D is also presented by defining the turn-on condition.The results of the model are verified by the numerical simulator DESSIS-ISE.

A continuous analytic channel potential solution to doped symmetric double-gate MOSFETs from the accumulation to the strong-inversion region

A continuous yet analytic channel potential solution is proposed for doped symmetric double-gate （DG） MOSFETs from the accumulation to the strong-inversion region. Analytical channel potential relationship is derived from the complete 1-D Poisson equation physically, and the channel potential solution of the DG MOSFET is obtained analytically. The extensive comparisons between the presented solution and the numerical simulation illustrate that the solution is not only accurate and continuous in the whole operation regime of DG MOSFETs, but also valid to wide doping concentration and various geometrical sizes, without employing any fitting parameter.

Analytical Modeling of Threshold Voltage for Double-Gate MOSFET Fully Comprising Quantum Mechanical Effects

The analytical solutions to 1D Schrdinger equation (in depth direction) in double gate (DG) MOSFETs are derived to calculate electron density and threshold voltage.The non uniform potential in the channel is concerned with an arbitrary depth so that the analytical solutions agree well with numerical ones.Then,an implicit expression for electron density and a closed form of threshold voltage are presented fully comprising quantum mechanical (QM) effects.This model predicts an increased electron density with an increasing channel depth in subthreshold region or mild inversion region.However,it becomes independent on channel depth in strong inversion region,which is in accordance with numerical analysis.It is also concluded that the QM model,which barely considers a box like potential in the channel,slightly over predicts threshold voltage and underestimates electron density,and the error increases with an increasing channel depth or a decreasing gate oxide thickness.

An improvement to computational efficiency of the drain current model for double-gate MOSFET

As a connection between the process and the circuit design, the device model is greatly desired for emerging devices, such as the double-gate MOSFET. Time efficiency is one of the most important requirements for device modeling. In this paper, an improvement to the computational efficiency of the drain current model for double-gate MOSFETs is extended, and different calculation methods are compared and discussed. The results show that the calculation speed of the improved model is substantially enhanced. A two-dimensional device simulation is performed to verify the improved model. Furthermore, the model is implemented into the HSPICE circuit simulator in Verilog-A for practical application.

A deterministic method study of the impact of the Pauli principle in double-gate MOSFETs

The Pauli principle is included in a multisubband deterministic solver for two-dimensional devices without approx- imations. The nonlinear Boltzmann equations are treated properly without compromising on accuracy, convergence, or CPU time. The simulation results indicate the significant impact of the Pauli principle on the transport properties of the quasi-2D electron gas, especially for the on state.

A Complete Surface Potential-Based Core Model for Undoped Symmetric Double-Gate MOSFETs

A surface potential-based model for undoped symmetric double-gate MOSFETs is derived by solving Poisson＇s equation to obtain the relationship between the surface potential and voltage in the channel region in a self-consistent way. The drain current expression is then obtained from Pao-Sah＇s double integral. The model consists of one set of surface potential equations,and the analytic drain current can be evaluated from the surface potential at the source and drain ends. It is demonstrated that the model is valid for all operation regions of the double-gate MOSFETs and without any need for simplification （e. g., by using the charge sheet assumption） or auxiliary fitting functions. The model has been verified by extensive comparisons with 2D numerical simulation under different operation conditions with different geometries. The consistency between the model calculation and numerical simulation demonstrates the accuracy of the model.

高压大功率SiC MOSFETs短路保护方法

碳化硅(SiC)MOSFETs短路承受能力弱,研究其短路保护方法成为保障电力电子设备安全运行的重要课题。现有方法大多围绕低压小功率SiC MOSFETs,然而随着电压和功率等级的提升,器件特性有所差异,直接套用以往设计难以实现高压大功率SiC MOSFETs的快速、可靠保护。该文首先详细研究了几种常用短路检测方法;其次基于高压大功率SiC MOSFETs器件特性,深入对比分析了不同短路检测方法的适用性,提出一种阻容式漏源极电压检测和栅极电荷检测相结合的短路保护方法;最后搭建了实验平台验证所提方法的可行性。结果表明,提出的方法在硬开关短路故障(hard switching fault,HSF)下,保护响应时间缩短了1.4μs,短路能量降低了62.5%;且能可靠识别负载短路故障(fault under load,FUL)。

Two-dimensional analytical models for asymmetric fully depleted double-gate strained silicon MOSFETs

This paper develops the simple and accurate two-dimensional analytical models for new asymmetric double-gate fully depleted strained-Si MOSFET. The models mainly include the analytical equations of the surface potential, surface electric field and threshold voltage, which are derived by solving two dimensional Poisson equation in strained-Si layer. The models are verified by numerical simulation. Besides offering the physical insight into device physics in the model, the new structure also provides the basic designing guidance for further immunity of short channel effect and draininduced barrier-lowering of CMOS-based devices in nanometre scale.

Two-dimensional models of threshold voltage and subthreshold current for symmetrical double-material double-gate strained Si MOSFETs

The two-dimensional models for symmetrical double-material double-gate （DM-DG） strained Si （s-Si） metal-oxide semiconductor field effect transistors （MOSFETs） are presented. The surface potential and the surface electric field ex- pressions have been obtained by solving Poisson＇s equation. The models of threshold voltage and subthreshold current are obtained based on the surface potential expression. The surface potential and the surface electric field are compared with those of single-material double-gate （SM-DG） MOSFETs. The effects of different device parameters on the threshold voltage and the subthreshold current are demonstrated. The analytical models give deep insight into the device parameters design. The analytical results obtained from the proposed models show good matching with the simulation results using DESSIS.

Simulation of a Double-Gate Dynamic Threshold Voltage Fully Depleted Silicon-on-Insulator nMOSFET

A novel planar DGDT FDSOI nMOSFET is presented, and the operation mechanism is discussed. The device fabrication processes and characteristics are simulated with Tsuprem 4 and Medici. The back-gate n-well is formed by implantation of phosphorus at a dosage of 3 × 10^13 cm^-2 and an energy of 250keV and connected directly to a front-gate n^＋ polysilicon. This method is completely compatible with the conventional bulk silicon process. Simulation results show that a DGDT FDSOI nMOSFET not only retains the advantages of a conventional FDSOI nMOSFET over a partially depleted （PD） SOI nMOSFET--that is the avoidance of anomalous subthreshold slope and kink effects but also shows a better drivability than a conventional FDSOI nMOSFET.

Trench型N-Channel MOSFET低剂量率效应研究

基于抗辐射100V Trench型N-Channel MOSFET开展了不同剂量率的总剂量辐射实验并进行了分析,创新性提出了器件随低剂量率累积以及不同偏置状态下的变化趋势和机理,给出了器件实验前后的转移曲线和直流参数,进行了二维数值仿真比较,证明了实验和仿真的一致性。研究表明:随高剂量率的剂量增加,器件阈值电压(V_(TH))发生了明显负向漂移现象,导通电阻(R_(DSON))出现5%左右的降低,击穿电压(BV_(DS))保持基本不变;低剂量率下总剂量效应与高剂量率有明显不同,阈值电压漂移量减小,同时出现正向漂移现象;此时导通电阻(R_(DSON))和击穿电压(BV_(DS))较高剂量率变化量进一步下降。研究认为,低剂量率下器件界面缺陷电荷增加变多,使得阈值电压的漂移方向发生改变,同时低剂量率实验周期是高剂量率的500倍,退火效应也较高剂量率的明显,导致器件参数辐射前后差异性减小。

适用于SiC MOSFET的漏源电压积分自适应快速短路保护电路研究

SiC MOSFET因其高击穿电压、高开关速度、低导通损耗等性能优势而被广泛应用于各类电力电子变换器中。然而,由于其短路耐受时间仅为2~7μs,且随母线电压升高而缩短,快速可靠的短路保护电路已成为其推广应用的关键技术之一。为应对不同母线电压下的Si C MOSFET短路故障,文中提出一种基于漏源电压积分的自适应快速短路保护方法(drain-sourcevoltageintegration-basedadaptivefast short-circuit protection method,DSVI-AFSCPM),研究所提出的DSVI-AFSCPM在硬开关短路(hardswitchingfault,HSF)和负载短路(fault under load,FUL)条件下的保护性能,进而研究不同母线电压对DSVI-AFSCPM的作用机理。同时,探究Si CMOSFET工作温度对其响应速度的影响。最后,搭建实验平台,对所提出的DSVI-AFSCPM在发生硬开关短路和负载短路时不同母线电压、不同工作温度下的保护性能进行实验测试。实验结果表明,所提出的DSVI-AFSCPM在不同母线电压下具有良好的保护速度自适应性,即母线电压越高,短路保护速度越快,并且其响应速度受Si CMOSFET工作温度影响较小,两种短路工况下工作温度从25℃变化到125℃,短路保护时间变化不超过90 ns。因此,该文为Si CMOSFET在不同母线电压下的可靠使用提供一定技术支撑。

SiC MOSFET高温栅氧可靠性研究

碳化硅SiC(silicon carbide)具有优良的电学和热学特性,是一种前景广阔的宽禁带半导体材料。SiC材料制成的功率MOSFET(metal-oxide-semiconductor field-effect transistor)非常适合应用于大功率领域,而高温栅氧可靠性是大功率MOSFET最需要关注的特性之一。通过正压高温栅偏试验和负压高温栅偏试验对比了自研SiC MOSFET和国外同规格SiC MOSFET的高温栅氧可靠性。负压高温栅偏试验结果显示自研SiC MOSFET与国外SiC MOSFET的阈值电压偏移量基本相等,阈值电压偏移量百分比最大相差在4.52%左右。正压高温栅偏试验的结果显示自研SiC MOSFET的阈值电压偏移量较小,与国外SiC MOSFET相比,自研SiC MOSFET的阈值电压偏移量百分比最大相差11%。自研器件占优势的原因是在SiC/SiO2界面处引入了适量的氮元素,钝化界面缺陷的同时,减少了快界面态的产生,使总的界面态密度被降到最低。

漏源电压对SiC MOSFET阈值电压准确测量影响的研究

相较于Si器件,SiC MOSFET近界面氧化物陷阱区域更广,界面态陷阱密度高出2个数量级,大量陷阱不断俘获或释放电荷,导致阈值电压(Vth)随时间波动较大,因而Vth的准确重复测量成为难题。标准中阈值电压测量采用预处理的方法,保证每次测量时陷阱电荷状态的一致性,但标准中未考虑漏源电压影响预处理填充后的陷阱状态,导致阈值电压测试误差。针对该问题,首先通过测量不同漏源电压脉冲影响下的转移曲线,显示不同源漏电压对阈值电压的影响;然后,基于瞬态电流法分析了漏源电压对陷阱电荷状态的影响;进而,分析了漏源电压影响陷阱的机理;最后对比了不同漏源电压对阈值电压测量的影响。实验表明,漏源电压影响栅漏间电场正负,进而影响陷阱填充或释放电荷,导致阈值电压漂移。测量阈值电压时使用较小漏源电压可提高测量准确性,减小可靠性实验由测试因素造成的误差。

SiC MOSFET开关瞬态解析建模综述

在评估和优化半导体器件开关瞬态特性领域,解析模型因具有简单、直观、应用便捷等优点得到广泛研究。相较同等功率等级的硅基功率器件,碳化硅(silicon carbide,SiC)金属氧化物半导体场效应晶体管(metal-oxide-semiconductor field effect transistor,MOSFET)可以应用于更高开关速度,其开关瞬态特性更为复杂,开关瞬态解析建模也更加困难。该文总结现有的针对SiC MOSFET与二极管换流对的开关瞬态解析建模方法,在建模过程中依次引入各种简化假设,按照简化程度由低到高的顺序,梳理解析建模的逐步简化过程。通过对比,评估各模型的优缺点以及适用场合,对其中准确性、实用性都较强的分段线性模型进行详细介绍;之后,对开关瞬态建模中关键参数的建模方法进行总结与评价;最后,指出现有SiC MOSFET开关瞬态解析模型中存在的问题,并对其未来发展给出建议。

动态高温反偏应力下的SiC MOSFET测试平台及其退化机理研究

为研究SiC MOSFET在动态漏源应力下的退化机理,开发了一种具有dVds/dt可调功能、最高可达80 V/ns的动态反向偏置测试平台。针对商用SiC MOSFET进行动态高温反偏实验,讨论高电压变化率的动态漏源应力对SiC MOSFET电学特性的影响。实验结果显示,器件的阈值电压和体二极管正向导通电压增加,说明器件JFET区上方的栅氧层和体二极管可能发生了退化。通过Sentaurus TCAD分析了在高漏源电压及高电压变化率下平面栅型SiC MOSFET的薄弱位置,在栅氧层交界处和体二极管区域设置了空穴陷阱,模拟动态高温反偏对SiC MOSFET动静态参数的影响。

一种低耦合电容的高压SiC MOSFET驱动隔离电源设计

高压SiC MOSFET更快的电压变化率dv/dt,导致其驱动遭受更严重的共模干扰,而现有高隔离电压驱动电源大多又存在耦合电容高、共模瞬态抗扰度(CMTI)能力弱、转换效率低等问题,因此该文设计一种兼具高隔离电压、高转换效率的低耦合电容驱动隔离电源。首先,基于有源钳位反激变换器,提出一种驱动隔离电源耦合电容等效简化解析模型,并通过仿真、实验验证解析模型可行性;其次,基于该模型分析耦合电容影响因素及其优化方法,为低耦合电容的驱动电源设计提供参考;最后,通过实验评估所提低耦合电容高压SiC MOSFET驱动隔离电源性能。结果表明,该文驱动隔离电源额定转换效率约80%,工频耐压高达18 kV,且耦合电容不足2 pF,CMTI能力强。

N型MOSFET器件总剂量效应通用测试系统设计

抗辐照电机驱动器研发需要准确获取电桥电路金属-氧化物半导体场效应晶体管(Metal Oxide Semiconductor Field Effect Transistor,MOSFET)器件的总剂量效应失效阈值,电流-电压、电容-电压等离线测试方法,无法真实反映器件开关性能随累积剂量增加的连续变化过程。因此,针对MOSFET器件总剂量效应的在线测试需求,设计了基于高速信号采集及存储的通用化测试系统,具备被测样品驱动、高频信号采集、高速数据存储、数据模块管理等功能。利用典型商用MOSFET器件开展了总剂量效应测试,结果显示,当吸收剂量达598.08±41.54 Gy(Si)时,样品采集方波波形开始出现异常,低电平电压升高至0.82 V,高电平电压始终正常;随着累积剂量的增大,低电平电压持续性升高至1.08 V,并进一步升高至1.24 V,但器件开关功能保持正常;当累积剂量达1775.41±219.68 Gy(Si)时,采集波形跳变为2.93 V的直线,无方波信号输出,经判断MOSFET开关功能完全受损。

空间辐射环境下SiC功率MOSFET栅氧长期可靠性研究

利用等效1 MeV中子和γ射线对1200 V SiC功率MOSFET进行辐射,研究了电离损伤和位移损伤对器件的影响,并分析了辐射后器件栅氧长期可靠性。结果表明:中子辐射后器件导通电阻发生明显退化,与辐射引入近界面缺陷降低载流子寿命和载流子迁移率有关。时间依赖的介质击穿(TDDB)结果表明,栅泄漏电流呈现先增加后降低趋势,与空穴捕获和电子捕获效应有关。中子辐射后栅漏电演化形式未改变,但氧化层击穿时间增加,这是中子辐射缺陷增加了Fowler-Nordheim(FN)隧穿势垒的缘故。总剂量辐射在器件氧化层内引入陷阱电荷,使得器件阈值电压负向漂移。随后的TDDB测试表明,与中子辐射一致,总剂量辐射未改变栅漏电演化形式,但氧化层击穿时间提前。这是总剂量辐射在氧化层内引入额外空穴陷阱和中性电子陷阱的缘故。