Analytical Model for the Piecewise Linearly Graded Doping Drift Region in LDMOS

A novel 2D analytical model for the doping profile of the bulk silicon RESURF LDMOS drift region is proposed. According to the proposed model, to obtain good performance, the doping profile in the total drift region of a RESURF LDMOS with a field plate should be piecewise linearly graded. The breakdown voltage of the proposed RESURF LDMOS with a piecewise linearly graded doping drift region is improved by 58. 8%, and the specific on-resistance is reduced by 87. 4% compared with conventional LDMOS. These results are verified by the two-dimensional process simulator Tsuprem-4 and the device simulator Medici.

Improving breakdown voltage performance of SOI power device with folded drift region

A novel silicon-on-insulator（SOI） high breakdown voltage（BV） power device with interlaced dielectric trenches（IDT） and N/P pillars is proposed. In the studied structure, the drift region is folded by IDT embedded in the active layer,which results in an increase of length of ionization integral remarkably. The crowding phenomenon of electric field in the corner of IDT is relieved by the N/P pillars. Both traits improve two key factors of BV, the ionization integral length and electric field magnitude, and thus BV is significantly enhanced. The electric field in the dielectric layer is enhanced and a major portion of bias is borne by the oxide layer due to the accumulation of inverse charges（holes） at the corner of IDT.The average value of the lateral electric field of the proposed device reaches 60 V/μm with a 10 μm drift length, which increases by 200% in comparison to the conventional SOI LDMOS, resulting in a breakdown voltage of 607 V.

SPICE model of trench-gate MOSFET device

A novel simulation program with an integrated circuit emphasis（SPICE） model developed for trench-gate metal-oxide-semiconductor field-effect transistor（M OSFET）devices is proposed. The drift region resistance was modeled according to the physical characteristics and the specific structure of the trench-gate MOSFET device. For the accurate simulation of dynamic characteristics, three important capacitances, gate-to-drain capacitance Cgd, gate-to-source capacitance Cgsand drain-to-source capacitance Cds, were modeled, respectively, in the proposed model. Furthermore,the self-heating effect, temperature effect and breakdown characteristic were taken into account; the self-heating model and breakdown model were built in the proposed model; and the temperature parameters of the model were revised. The proposed model is verified by experimental results, and the errors between measured data and simulation results of the novel model are less than 5%. Therefore, the model can give an accurate description for both the static and dynamic characteristics of the trench-gate MOSFET device.

A New High Voltage SOI Device with a Nonuniform Thickness Drift Region and Its Optimization

A new SO1 high-voltage device structure with nonuniform thickness drift region （n-uni SOl） and its optimiza- tion design method are proposed. Owing to the nonuniform thickness drift region, the electric field in the SOl layer is modulated and the electric field in the buried layer is enhanced, resulting in an enhancement of breakdown voltage. An analytical model taking the modulation effect into account is presented to optimize the device structure. Based on the analytical model, the dependencies of the electric field distribution and breakdown voltage on the device parameters are investigated. Numerical simulations support the analytical model. The breakdown voltage of the n-uni SOl LDMOS with n = 3 is twice as high as that of a conventional SO1 while its on-resistance maintains low.

Novel 700 V high-voltage SOI LDMOS structure with folded drift region

A new high-voltage LDMOS with folded drift region （FDR LDMOS） is proposed. The drift region is folded by introducing the interdigital oxide layer in the： Si active layer, the result of which is that the effective length of the drift region is increased significantly. The breakdown characteristic has been improved by the shielding effect of the electric field from the holes accumulated in the surface of the device and the buried oxide layer. The numerical results indicate that the breakdown voltage of 700 V is obtained in the proposed device in comparison to 300 V of conventional LDMOS, while maintaining low on-resistance.

An analytical model for the drain-source breakdown voltage of RF LDMOS power transistors with a Faraday shield

An analytical model for the drain-source breakdown voltage of an RF LDMOS power transistor with a Faraday shield is derived on the basis of the solution of the 2D Poisson equation in a p-type epitaxial layer, as well as an n-type drift region by means of parabolic approximation of electrostatic potential. The model captures the influence of the p-type epitaxial layer doping concentration on the breakdown voltage, compared with the previously reported model, as well as the effect of the other device parameters. The analytical model is validated by comparing with a numerical device simulation and the measured characteristics of LDMOS transistors. Based on the model, optimization of LDMOS device parameters to achieve proper trade-off between the breakdown voltage and other characteristic parameters such as on-resistance and feedback capacitance is analyzed.

An analytical model for the surface electrical field distribution of LDMOSFETs with shield rings

An analytical model of an LDMOSFET with a shield ring is established according to the 2D Poisson equation. Surface electrical field distribution along the drift region is obtained from this model and the influence of shield length and oxide thickness on the electrical field distribution is studied. The robustness of this model is verified using ISE TCAD simulation tools. The breakdown voltage of a specific device is also calculated and the result is in good agreement with experimental data.